Xilinx XS - post- and pre-synthesis do not match

[sujithchakra]

Synthesis Problems

Hi,

I am using Xilinx XST to synthesize my design. Post-synthesis simulation is not matching pre-synthesis simulation. I figured out where the problem is. But I do not understand how to trouble shoot this.

Below is one of the always block in my design. In pre-synthesis simulation, if wb_we_i is not equal to 0, then the simulator executes the "else block" and assigns wb_dat_o with "8'bx" value. If it is 1 then simulator executes "if block". In post synthesis simulation, irrespective of the value of wb_we_i(0 or 1), the simulator executes only "if block". I do not understand why it is happening. Please help.

always @(posedge wb_clk_i)
begin
if (wb_we_i==0)
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= prer[ 7:0];
3'b001: wb_dat_o <= prer[15:8];
3'b010: wb_dat_o <= ctr;
3'b011: wb_dat_o <= rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= sr; // write is command register (cr)
3'b101: wb_dat_o <= txr;
3'b110: wb_dat_o <= cr;
3'b111: wb_dat_o <= 0; // reserved
endcase
else
case (wb_adr_i)
3'b000: wb_dat_o <= 8'bx;
3'b001: wb_dat_o <= 8'bx;
3'b010: wb_dat_o <= 8'bx;
3'b011: wb_dat_o <= 8'bx;
3'b100: wb_dat_o <= 8'bx;
3'b101: wb_dat_o <= 8'bx;
3'b110: wb_dat_o <= 8'bx;
3'b111: wb_dat_o <= 8'bx;
endcase
end

I am using ModelSim PE Verilog student edition to simulate the netlist and it is throwing an error "# ** Warning: Design size of 47649 statements or 3176 leaf instances exceeds ModelSim PE Student Edition recommended capacity.
# Expect performance to be quite adversely affected.". Is this a possible reason? Please help.

Thanks

 

[goshka]

Re: Synthesis Problems

Look at xst rtl schematic.
may be,

reg cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7;
always @(posedge wb_clk_i) 
begin 
 if (wb_we_i = 1'b0) 
 	case (wb_adr_i) // synopsis parallel_case 

 	case (wb_adr_i) // synopsis parallel_case 
		3'b000: wb_dat_o <= prer[ 7:0]; 
		3'b001: wb_dat_o <= prer[15:8]; 
		3'b010: wb_dat_o <= ctr; 
		3'b011: wb_dat_o <= rxr; // write is transmit register (txr) 
		3'b100: wb_dat_o <= sr; // write is command register (cr) 
		3'b101: wb_dat_o <= txr; 
		3'b110: wb_dat_o <= cr; 
		3'b111: wb_dat_o <= 0; // reserved 
	endcase 
 else 
	case (wb_adr_i)                         // synopsis parallel_case 
		3'b000: wb_dat_o <= 8'bx; 
		3'b001: wb_dat_o <= 8'bx; 
		3'b010: wb_dat_o <= 8'bx; 
		3'b011: wb_dat_o <= 8'bx; 
		3'b100: wb_dat_o <= 8'bx; 
		3'b101: wb_dat_o <= 8'bx; 
		3'b110: wb_dat_o <= 8'bx; 
		3'b111: wb_dat_o <= 8'bx; 
	endcase 
end

in wihsbone write cycle case, wb_slave data regs also may connect to sdat_o (ignored buy wb_master):

always @(posedge wb_clk_i) 
begin 
 	case (wb_adr_i) // synopsis parallel_case 
		3'b000: wb_dat_o <= prer[ 7:0]; 
		3'b001: wb_dat_o <= prer[15:8]; 
		3'b010: wb_dat_o <= ctr; 
		3'b011: wb_dat_o <= rxr; // write is transmit register (txr) 
		3'b100: wb_dat_o <= sr; // write is command register (cr) 
		3'b101: wb_dat_o <= txr; 
		3'b110: wb_dat_o <= cr; 
		default: wb_dat_o <= 8'h0; // reserved 
	endcase 
end

use bufif1 keyword:

reg cs0, cs1, cs2, cs3, cs4, cs5, cs6, cs7;
always @(posedge wb_clk_i) 
begin 
 if (wb_we_i = 1'b0) 
 	case (wb_adr_i) // synopsis parallel_case 
		3'b000: cs0 <= 1'b1; 
		3'b001: cs1 <= 1'b1; 
		3'b010: cs2 <= 1'b1; 
		3'b011: cs3 <= 1'b1; // write is transmit register (txr) 
		3'b100: cs4 <= 1'b1; // write is command register (cr) 
		3'b101: cs5 <= 1'b1; 
		3'b110: cs6 <= 1'b1; 
		3'b111: cs7 <= 1'b1; // reserved 
	endcase 
 else
 	begin
 	cs0 <= 1'b0; 
 	cs1 <= 1'b0;
 	cs2 <= 1'b0;
 	cs3 <= 1'b0;
 	cs4 <= 1'b0;
 	cs5 <= 1'b0;
 	cs6 <= 1'b0;
 	cs0 <= 1'b0;
 	end
end 

bufif1 buf0[8:0] ( wb_dat_o,  prer[ 7:0], cs0); 
bufif1 buf1[8:0] ( wb_dat_o,  prer[15:8], cs1); 
bufif1 buf2[8:0] ( wb_dat_o,  ctr,        cs2); 
bufif1 buf3[8:0] ( wb_dat_o,  rxr ,       cs3); 
bufif1 buf4[8:0] ( wb_dat_o,  sr ,        cs4); 
bufif1 buf5[8:0] ( wb_dat_o,  txr ,       cs5); 
bufif1 buf6[8:0] ( wb_dat_o,  cr ,        cs6); 
bufif1 buf7[8:0] ( wb_dat_o,  8'h0 ,      cs7);

 

[littlebu]

Synthesis

hi sujithchakra

during the synthesis, tools will not try to solve like " <= 'bx" logic. that why somebody like to add "'bx" logic just for function debug.

so i think your circuit will not include ELSE bench after synthesis.

Thanks

 

[cherjier]

Synthesis Problems

Hi sujithchakra,

well, your always block seem to be a little bit odd especially after the else statement but i think this will not cause any problem on synthesis.

i suspect the problem is cause by "case (wb_adr_i)"
what is the width of the wb_adr_i? if wb_adr_i is define as 3bits than the always block is ok but if u define wb_adr_i more than 3bits then i think the always block might cause a problem in synthesis. try change your code to "case (wb_adr_i[2:0])" on both if and else statement.

 

[sujithchakra]

Re: Synthesis

Thanks littlebu. Your suggestion helped me.

 

[sujithchakra]

Re: Synthesis Problems

Hi,

The problem is solved. I replaced 8'bx by 8'bz because there is nothing like 8'bx in hardware. Since 8'bx represents don'tcares, synthesis tool chooses some optimal value in place of 8'bx. Now my post synthesis simulation works fine.

Thank you all for your suggestions.