Xilinx Spartan IIe internal connection of GSR and GTS quest

gsr xilinx

Hi,

does any body know how to internally connect the Global Set Reset Signal of a spartan IIe device??

My problem is that i haven't got a reset input on my application. The VHDL code of the earlier project was written for a ORCA and is now ported to the spartan. In the earlier project an external reset pin was used, now there isn't one.

So I want to connect the internally generated GSR signal from the Startup circuit as a source to drive all internal reset signals.

What do I have to do??

Any help is appreciated!!

Thanks folks,

aOxOmOx

xilinx gsr

What do you have to do? Been able to reset your device every now and then or only power it up in a known state?

I wouldn't use the GSR if you only want to power it up in a known state, is bloody slow and takes ages to propagate through the chip. If you write your VHDL/Verilog properly your synthesizer will infer the proper FFs to use and they will power up in the 'reset' value.

You can use FPGA Editor to see what the value of your registered signal is after power-up.

-maestor

where to connect gts and gsr in cpld

Thanks Maestor,

my problem is that all vhdl components require a reset signal to be input. But I have no output to drive this signal. that's why i thought of some how put the GSR signal as a source to an internal reset signal that is then connectet to all components.
At the moment my reset net is floating (only inputs).

I need to know how to connect to gsr in order to translate it to reset.

Xilinx tells something about using STARTUP_SPARTAN where a virtual gsr signal is connected to a secondary reset net. but I didn't get how to connect to gsr as an input.

any ideas,

aOxOmOx

startup_spartan

Hi,

If you only want to reset your logic at power up, then you can use a dummy internal signal as your reset.

You write your other component as normal VHDL. The synthesizer will infer the global reset automatically. Inside of xilinx FPGA, the power on reset is actually ored with the outside reset signal. So if you put your internal reset signal at '0', you'll only get reseted only when your FPGA is configured.

I've done this in virtex II. I guess it should be the same for your spartan.

regards

gts,gsr in cpld

Hi all,

got the answer some days ago.

The answer is called ROC:

component ROC
-- synthesis translate_off
generic (WIDTH : Time := 100 ns);
-- synthesis translate_on
port (O : out std_ulogic := '1');
end component;


the output in the port map can be routed to the internal rest signal.
When the SPARTAN has been booted correctly the internal ROC circuit will set up the whole FPGA by asserting SET/RESET and later the global reset signal. this asserted signal RESET (not "/Reset") can be taken from the component ROC as an output and use to setup all state machines.

spartan iie startup

Hi Aoxomox,

I am pretty sure the ROC module (Reset on Configuration or something like that) is not synthesizable or... have things changed and now tools like Synplify or Precision use it to infer a Reset after Configuration?

Correct if I am wrong but maybe this ROC module has helped you to write a better VHDL/Verilog and now your FSMs and FFs reach a known state after configuration.... :roll:

-maestor

pin gsr gts

Dear maestor
I had reffered to Xilinx DOc lib.pdf and I found twp types of ROC (ROC &ROCBUF) that can be used for the purpose that Aoxomox want to use.

gsr verilog

Al Farouk man,

I am not sure if we are talking about the same thing but having a look to this AGAIN it just confirmed what I thought :

**broken link removed**

The ROC is ONLY for simulation and what is worse it's X!linx specific so no portable to another vendors.

-maestor

fpga spartan global reset

Dear maestor
Thanks for your interestto clarify the issue for us. In the lib.pdf note that he switch the synthesizer on before the component

VHDL Instantiation Code
component ROC
-- synthesis translate_off
generic (WIDTH : Time := 100 ns);
-- synthesis translate_on (synthesis ON)
port (O : out std_ulogic := ’1’);
end component;

to Test the issue I had written a simple VHDL and use the ROC component inside it then synthesized it using Le@nardo and write the out as VHDL file again. the synthesizer accept it as a vaild library xilinx component and it appears in the out structure VHDL file rom le@nardo. kindly find attached the RTL VHDL file and the output VHDL from Le@nardo. check it and reply with your point of view.

Thanks

xilinx gsr

It is seems that it is not syenthesizable as when I Checked the Le@nardo report I saw that the ROC component is treated as Black Box component.

1- Leanardo
*******************************************************

Cell: ROC_100ns View: INTERFACE Library: work

*******************************************************


Number of ports : 1
Number of nets : 0
Number of instances : 0
Number of references to this view : 1

Total accumulated area :
Black Box ROC_100ns : 1
*******************************************************

Also the xilinx implementation gave the following error

2- Xilinx Implementation

Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'u1' with type 'ROC_100ns' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'ROC_100ns' is not supported in target 'spartan2'.

NGDBUILD Design Results Summary:
Number of errors: 1
Number of warnings: 0

One or more errors were found during NGDBUILD. No NGD file will be written.

Tks

xilinx connection

In summary, ROC is not synthesizable, is NOT a real element of a Xilinx FPGA and can be used to help you during simulation to check if all your FFs will power up in the right state.

-maestor

xilinx vhdl instantiate gsr

Hi folks,

finally I found the correct answer:

The element "ROC" is only for simulation purpose.
It will not be synthesized in the final design.

The second element is called "ROCBUF" and can be
used as an internal reset generator.
At the end of the boot procedure, when all necessary
bits have been send to the FPGA an internal startup
sequence is started. Then the GTS and GSR signals
will be asserted to allow the general function of the FPGA.
With "ROCBUF" an internal signal can be accessed
that signalls that the startup procedure is finished. I now
use this signal as RESET.


thanks for all your replies.
aOxOmOx