I am testing on my project using Xilinx Spartan-3E. When I try to ping the FPGA from my PC (using a fixed IP & MAC address) The device reply to my ping. But as time slipped by, it will stop responding to ping (and ARP) requests. And reset of the device is needed.
How does this happens? Does this have to do with the setting of the router??
You may be experiencing crippleware. The Spartan-3E Starter Kit User Guide says this:
The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx website at:
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I am testing on my project using Xilinx Spartan-3E. When I try to ping the FPGA from my PC (using a fixed IP & MAC address) The device reply to my ping. But as time slipped by, it will stop responding to ping (and ARP) requests. And reset of the device is needed.
How does this happens? Does this have to do with the setting of the router??
can i ask for the source code of your project? we are also doing a project that deals with the ethernet of the spartan 3e. and we are having a hard time figuring out how the stuff works. and we are actually on our fifth year and also having our thesis project. could we ask your help to lessen our burden and we can graduate
If you would like a VHDL code for Ethernet MII, Queensland University has developed an IP stack that included MII operations. Perhaps you can check it out.
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This had been what I used as the base for my design. As for my implementation, it was added with some extra stuffs & I can hardly recall everything since it was done years ago