Xilinx post synthesis simulation Isim

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SharpWeapon

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Hello,

I have a design where behavioral simulation is different from post synthesis simulation. I tried to correct all the codes that might cause this difference, yet the same. The thing that REALLY annoys me is I am unable to debug each stage of my code in post synthesis simulation. Is there a way that I can check my post synthesis simulation stage by stage as I do in behavioral simulation?

Btw, when I do that post synthesis simulation, first I generate my file using Generate post synthesis simulation and wrote a test-bench for it and simulate it the same way as behavioral simulation. I have seen a different way of doing it in xilinx page, but didn't work for me. Would love to hear also if there is an easy way of doing it rather than doing the whole synthesis and post synthesis thing for just one semicolon correction.

Thanks!
 

I've also seen differences due to testbench timing that resulted in data showing up later in a netlist level simulation than the corresponding behavioral RTL testbench. Most of these cases occurred due to delta time issues caused by the gate level netlist models. This is why I normally run inputs into the DUT from the testbench either on the opposite edge of the clock or add a transport delay to the signals. These instances weren't cases of functional errors just differences in when data entered design, thereby resulting in different outputs that no longer matched the behavioral simulation.
 
Thank you TrickyDicky for the reply, but my design is many vhd files, it is even impossible to post a traceable fragment.

Hey ads-ee, thank you. I think that is right on answer, when I play with the enable time of DUT from the test bench, there is a noticeable difference. I will try opposite edge and transport delay trick.

But I am still wondering, how should one check what causes the mismatch between the simulations, I mean which line of code or which module or sth?
 
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main question - is your entire design synchronous -ie. every signal is generated inside a clocked process? if not, you are relying on LUT delays to be low enough to produce the correct results - in simulation the delay is always 0, but for the real circuit/timing sim, it will have a delay value.

Does the design meet your timing requirements?
 
Most of my signals are generated inside a clocked process but there are few which I intentionally make them asynchronous. And yes, it perfectly meets my timing requirement!

But what I really wanted is I want a way of checking my output at each stage in post synthesis simulation, that way I can spot on the exact problem/module with problem. Is there such a way?

PS: some of the output data of post synthesis simulation are same with the behavioral simulation. That is why I wanted to check which module caused a problem.
 

force keep hierarchy in the synthesis options. This will keep all module boundaries in place in the synthesized netlist. You can also synthesize bottom up.

- - - Updated - - -



The bottom option is set to yes
 

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I kinda found the module that is not working. I have a multiplier in the middle, the multiplier reads the first input, from the file and copy it to memory and take the other input from previous modules. I am using DSP48E1 for multiplication. The funny part is the result(post synthesis simulation) is the same as the simulation for values equal to one from file, and different for all non-one values. Here is how I read the data from file:

Code: 
entity Memory is
	generic(
			memDepth:integer:=16;
			memWidth:integer:=16;
			fileName: string:="~\test.txt"
		);
	port(			
		CLK:in STD_LOGIC;
		readEn:in STD_LOGIC;
		memAddress:in integer range 0 to memWidth-1;
		dataOut:out STD_LOGIC_VECTOR(memWidth-1 downto 0)		
	 );
end Memory;

architecture Behavioral of Memory is

type mem is array(memDepth-1 downto 0) of STD_LOGIC_VECTOR(memWidth-1 downto 0);

function loadRom(fileName: string) return mem is	
	file toBeRead: TEXT open read_mode is fileName;
	variable inLine: line;
	variable temp: STD_LOGIC_VECTOR(memWidth-1 downto 0):= (others=>'0');
	variable index: integer:=0;
	variable endOfFile: STD_LOGIC;
	variable ROM: mem;
begin
	for i in mem'range loop
		if not(endfile(toBeRead)) then
			readline(toBeRead, inLine);
			read(inLine, temp);
			ROM(index):=temp;	
			index:=index+1;
		else
			endOfFile:='1';
		end if;			
	end loop;
	return ROM;
  end loadRom;

constant ROM: mem := loadRom(fileName);
begin	
	process(CLK)
	begin 
		if (CLK'event and CLK='1')then 
			if(readEn='1') then 
				dataOut<=ROM(memAddress);
			end if;
		end if;
	end process;
end Behavioral;
Do you see any bug in my file reading, not synthesizable? Or should I change the slice to *? Thanks!

PS: In synthesizing the multiplier module, I have this warning:
Code: 
"Due to other FF/Latch trimming, FF/Latch <dataOut_0> (without init value) has a constant value of 0 in block <Memory>. This FF/Latch will be trimmed during the optimization process."
for almost all the dataOut. Does the optimization change the value of my dataOut?
 
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