Pete.Cannan
Newbie level 2
Dear Friends
I'm working on ML605 development board to benefit from its PCIe facilities. I tried to synthesize and implement PIO application example provided by Xilinx. When I use the bitstream provided by Xilinx for PIO (xapp1022), I can detect the PCIe endpoint in Device Manager and can communicate with the board.
When I implement PIO with an appropriately generated CORE, I fail to detect the PCIe endpoint.
I need your helps and comments to resolve my problem.
TIA
Pete Cannan
I'm working on ML605 development board to benefit from its PCIe facilities. I tried to synthesize and implement PIO application example provided by Xilinx. When I use the bitstream provided by Xilinx for PIO (xapp1022), I can detect the PCIe endpoint in Device Manager and can communicate with the board.
When I implement PIO with an appropriately generated CORE, I fail to detect the PCIe endpoint.
I need your helps and comments to resolve my problem.
TIA
Pete Cannan
