graphene
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Once I synthesise a code with an entity and module, the RTL schematic and technology schematic comes with a black box of input and outports.
However, when I change the ports or lets say add/delete ports they dont get updated in Xilinx ISE webedition 14,7 after synthesis.
I tried clearing the cache through Project > cleanup files. Still no go.
It reallys drains my time and everytime I had to create a new project just for this reason. Any suggestion?
Thanks in advance.
However, when I change the ports or lets say add/delete ports they dont get updated in Xilinx ISE webedition 14,7 after synthesis.
I tried clearing the cache through Project > cleanup files. Still no go.
It reallys drains my time and everytime I had to create a new project just for this reason. Any suggestion?
Thanks in advance.