Xilinx ISE question ????

[dibl01]

bugs in ise 9

Hi, Friends,

I am setting up a FPGA design flow for study. Right now, modelsim and sy*plify pro are working. I am still looking for Place_and_Route tool for Xilinx fpga. I wonder do I need to get xilinx ise aliance or the free ise webpack will good for me?

 

[buzkiller]

xilinx ise old versions 8

Depends on the device you are planning to use. Look here for more details :
https://www.xilinx.com/ise/products/webpack_config.htm

regards,
Buzkiller.

 

[dibl01]

ise webpack io planning

Depends on the device you are planning to use. Look here for more details :
h**p://www.xilinx.com/ise/products/webpack_config.htm

regards,
Buzkiller.

Thank you! According to sy*plify's manual, I will need Design Manager M3 or M4 to do P&R for xilinx virtex-II. I am not sure whether webpack ise includes the design manager.


Here is what xilinx says about webpack:

ImplementationTools

iMPACT
FloorPlanner
Xilinx Constraints Editor
Timing Driven Place & Route

There is no mention of design manager

Maybe you could enlight me on this issue.

Thank you!

 

[igorsat]

current source xilinx

You will need ISE 4.2 and the latest SP. Only the smaller Virtex-II devices are supported with the webPack. Previous versions of ISE (3.3 and 4.1) have too many bugs with the Virtex-II, so I advice you to use ISE 4.2. I don't use webPack, but I think design manager should be part of the package. It would be logical.

 

[padspcb]

synplify support for xilinx navigator 4.2

Hi
I have both, and they are basically the SAME
only webpack is licenceless
You can always download the devices you need
Grab the whole stuff...

Hint:
You can program the devices using Paralel mode.
Basically you need the \PROGRAM, \WR , \CS and CCLK.
You realy dont need INIT, BUSY and other stuff.
Suppose it has 8KBytes of programming info, you
1- Set CCLK High
2- PRORAM Low
3- Flip CCLK at least one time
4- Release PROGRAM
5- Now the magic, Clock CCLK at least more than the required memory
so you get sure that all will be erased.
6- Assert CS and WR
7- Program the chip, by outputing d0-7 and cycling cclk
8- release all pins
9- You may now reuse CS, WR, D0~7 for your app
10- Read a test stuff iside your asic, like set a port and read back
to make sure device programmed...
Dont waste eproms and other stuff
Best
PADS

 

[buzkiller]

ise question model

Design Manager is a part of WebPack. What is the exact device you plan to use ?

regards,
Buzkiller.

 

[dibl01]

xilinx impact webpack vs ise

Thank you all for the information:

I downloaded lastest webpack ise 4.2wp3 from xilinx web site. To my surprise, it supports the virtex-E xcv100e we have in the lab. Now xilinx include project navigator instead of old design manager in ise. The only drawback of webpack ise is the 300k gate design limit. However, for now it is ok to use with synplify pro to implement some relative small design. I also found ise 4.2 fundation on a ftp. But I do not how to get the latest service pack. For now, I will stick with webpack.

DIBL01

 

[Erich]

xilinx student edition 4.2i free download

Q: I am setting up a FPGA design flow for study. Right now, modelsim and sy*plify pro are working. I am still looking for Place_and_Route tool for Xilinx fpga. I wonder do I need to get xilinx ise aliance or the free ise webpack will good for me?

A: Depends on the design!
For normal things the ISE Webpack from xilinx is perfect. And is legal (you just download the program from xilinx). However if you are making a big design (above 300 IO) then you will need definetly to buy or obtain the higher EDA tools
Now about PAR tool in the processes for current source you will find for
PAR the floorplanner and the FPGA editor. These programs apply for the
ISE webpack