FlyingDutch
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Hello,
I just has finished study Xilinx documentation for "Fast Fourier Transform v9.1" - see link:
https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_1/pg109-xfft.pdf
and I wasn't able to find information about "window filtering". It seems that such function isn't implemented. I am wondering why?
The same situation with Gowin "FFT" IP core. I thought that such importent function should be implemented in "FFT" IP Core.
I found such article about implementing "window filtering" in FPGA (VHDL):
https://discourse.world/h/2018/10/23/Features-of-window-filtering-on-FPGA
Could somebody give me clues about implementation of "window filtering" in FPGA (especially in Verilog).
Thanks in advance and regards
I just has finished study Xilinx documentation for "Fast Fourier Transform v9.1" - see link:
https://www.xilinx.com/support/documentation/ip_documentation/xfft/v9_1/pg109-xfft.pdf
and I wasn't able to find information about "window filtering". It seems that such function isn't implemented. I am wondering why?
The same situation with Gowin "FFT" IP core. I thought that such importent function should be implemented in "FFT" IP Core.
I found such article about implementing "window filtering" in FPGA (VHDL):
https://discourse.world/h/2018/10/23/Features-of-window-filtering-on-FPGA
Could somebody give me clues about implementation of "window filtering" in FPGA (especially in Verilog).
Thanks in advance and regards