xilinx DCM for clock divider

I need to divide the 50 MHz clock to 1.5 Mhz and 0.5MHz both with with 50% duty cycle. For this I want to use Xilinx DCM.

To get 0.5MHz (2 us) from 50Mhz (20 ns) I need to divide input clock by 100 but DCM can divide only till 16.

To get 1.5 Mhz (0.66666 us) from 50Mhz (20 ns) I need to divide input clock by 33.3333 but DCM doesn't have this value to divide.

Can anyone please tell me how to implement it achieve this two clocks?

Step 1: check the datasheet for your chosen fpga to see what the allowed input frequencies are for the DCM.
Step 2: cascade 2 DCM's to obtain larger division ratios. First divide by 5 (50 MHz in ==> 10 MHz out), then divide by 10 (10 MHz in==> 0.5 MHz out)

I'm assuming here that the fpga you did not specify will be able to handle 10 MHz input on the DCM. And you may want to check that, because some Xilinx fpga can take 10 MHz input on the DCMN, and some don't. Older spartan-3's only take 18 MHz or higher. So if you have one of those you're boned. 18 MHz / 16 ... higher than 0.5 MHz.

As an alternative to using DCM for clock division you can use clock enable signals. If you don't know clock enables, google for "xilinx clock enable CE" for some ideas.

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Hey wait, I just noted the logical progression of your posts. Well, alogical progression really, but who cares.

First you used some gated clock as divider, then K-J suggested to use clock enables, then <something>, and then you want to use DCM's for clock division. I interpret that as "I tried clock enables but failed, so now I will try DCMs". If that is the case, I suggest you try harder to get clock enables to work. If only because for this particular problem (*) it is the right solution.

*) assuming this thread is about the exact same thing as your other thread "VHDL clock divider warning". But of course it will be the exact same thing because humans are predictable that way.

Yes, you are correct mrfibble. I am new to vhdl. Do you think I need to use clock enable to get both the desired clocks (1.5 MHz and 0.5 Mhz)?

Yup. Use clock enables.

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The 1.5 MHz one might be a bit tricky, because with integer division you can't get 1.5 MHz from 50 MHz. So you will not get exactly 50% duty cycle that way, but that is probably not an issue. If you think it is a problem, please clarify why.