spman
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Hi,
I want to generate a floating point adder by Xilinx core generator. My data isn't the standard precision floating point. I want to use a custom precision with 28 bits. But the problem is that the core for custom precision doesn't use dsp slices and is implemented with logic only. The design needs lots of adders and must be implemented with high frequency constraints. What should I do to use dsp slices?
My FPGA is Virtex6 xc6vlx240t.
Thanks in advance
I want to generate a floating point adder by Xilinx core generator. My data isn't the standard precision floating point. I want to use a custom precision with 28 bits. But the problem is that the core for custom precision doesn't use dsp slices and is implemented with logic only. The design needs lots of adders and must be implemented with high frequency constraints. What should I do to use dsp slices?
My FPGA is Virtex6 xc6vlx240t.
Thanks in advance