Xilinx CoreGen core in ISE 14.7: sim OK but synthesis is instantiating empty module

Hello,

I already asked this question in Xilinx forums, but have not received an answer yet... Maybe you guys can help me!

I'm trying to instantiate a floating point 5.0 core generated by 'Core Generator and architecture wizard'...

In my ISE 14.7 project (targeting xc6slx4), I did Project -> New source -> IP (Core Generator and architecture wizard) -> and selected Floating Point 5.0.
I configured the core in the wizard (multiplier, etc...) then generated. It's named 'fp_mul'.
In the ipcore_dir created, there is a fp_mul.vhd apparently used for simulation. Made a test bench and it is working fine in simulation.

The problem is that when I actually try to instantiate and synthesize the core: it looks like it's trying to use the same file used for simulation, and therefore, it is like using an empty file because of the "-- synthesis translate_off / on" attributes. So no error but it is clearly not implemented...

I instantiated the core like it is done in the template file .vho.

Why can I do to solve this issue ? How can I actually instantiate the core?
Thanks a lot,

Ril

- - - Updated - - -

Well, nevermind....

After regenerating the core for the Nth time..... it is finally working properly! Note sure what was happeninh...

When you use the core you should specify that the top level file instantiates the core but you should add the .xco file not any of the .vhd files generated by Core Generator.
It should look something like this:

Notice the top level has the xco file as the IP core