[SOLVED] Xilinx clock divider using DCM

[CataM]

I want to divide the input clock frequency provided by my Spartan3-xc3s200 by 2. I used the DCM to do that.

I do not know why do they give me the CLK0 output since I do not want to use it anymore. I want to use the CLKDV output. Is it possible to leave it unconnected ?



Thanks in advance !

 

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Just connect it to open, i.e. CLK0_OUT => open,

 

[CataM]

Thank you. By the way, I have connected a signal to LOCKED_OUT and the inverted signal to RST_IN, what do you think about that? Correct ? Incorrect ? I know in the datasheet they say that RST_IN should be activated on the transition from 1 to 0 of the LOCKED_OUT... but is it ok that way too ?