OvErFlO
Full Member level 3
Xilinx CLKDLL Error
What's mean this error :
# ** Warning: Timing Violation Error : Input Clock Period of3 ns on the CLKIN port of CLKDLL instance * exceeds allotted value of 0.04 ns at simulation time 13 ns.
How can I resolve it ?
I have write this VHDL Code :
with a ClkIN of 24Khz
What's mean this error :
# ** Warning: Timing Violation Error : Input Clock Period of3 ns on the CLKIN port of CLKDLL instance * exceeds allotted value of 0.04 ns at simulation time 13 ns.
How can I resolve it ?
I have write this VHDL Code :
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;
entity test_dll is
Port ( in_clk : in std_logic;
out_clk_dll1 : out std_logic;
out_clk_dll2 : out std_logic);
end test_dll;
architecture Behavioral of test_dll is
signal CLKIN, CLK, CLK0, LOCKED,net1 : std_logic;
component CLKDLL
port (CLKIN, CLKFB, RST : in STD_LOGIC;
CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;
component IBUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;
component OBUF
port (I : in STD_LOGIC; O : out std_logic);
end component;
begin
U1: IBUFG port map (I=>IN_CLK, O=>CLKIN);
U2: CLKDLL port map (CLKIN=>CLKIN, CLKFB=>CLKIN, RST=>'0', CLK0=>net1, CLK2X=>LOCKED);
U3: OBUF port map (I=>net1, O=>CLK0);
out_clk_dll1 <= CLK0;
out_clk_dll2 <= LOCKED;
end Behavioral;with a ClkIN of 24Khz