Xilinx CLKDLL: Timing Violation Error in VHDL code

[OvErFlO]

Xilinx CLKDLL Error

What's mean this error :

# ** Warning: Timing Violation Error : Input Clock Period of3 ns on the CLKIN port of CLKDLL instance * exceeds allotted value of 0.04 ns at simulation time 13 ns.

How can I resolve it ?

I have write this VHDL Code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity test_dll is
    Port ( in_clk : in std_logic;
           out_clk_dll1 : out std_logic;
			  out_clk_dll2 : out std_logic);
end test_dll;

architecture Behavioral of test_dll is

			signal CLKIN, CLK, CLK0, LOCKED,net1 : std_logic;
 
			component CLKDLL
			      port (CLKIN, CLKFB, RST : in STD_LOGIC;
			      CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
			end component;
 
			component IBUFG
			      port (I : in STD_LOGIC; O : out std_logic);
			end component;
 
			component OBUF
			      port (I : in STD_LOGIC; O : out std_logic);
			end component;

begin

			U1: IBUFG port map (I=>IN_CLK, O=>CLKIN);
			U2: CLKDLL port map (CLKIN=>CLKIN, CLKFB=>CLKIN, RST=>'0', CLK0=>net1, CLK2X=>LOCKED);
			U3: OBUF port map (I=>net1, O=>CLK0);

			out_clk_dll1 <= CLK0;
			out_clk_dll2 <= LOCKED;

end Behavioral;

with a ClkIN of 24Khz

 

[yeewang]

Xilinx CLKDLL Error

CLKDLL has a input frequency range from 25M ~ xxM, i don't remember. your 24KHz clkin is ridiculous. no offending.

 

[AMCC]

Re: Xilinx CLKDLL Error

In the most 'Slow' option, CLKIN min is 1Mhz.
I also notice that you are using the SAME signal for CLKIN and CLKFB. This will probably don't work since DCM MAY not be able to match lock phases (this is route dependant).

If you are using a 24kHz frequency Don't used DCM. If you are tryng to double the frequency (as it seems from your VHDL) check for the possibility of using the same clock but inverted or using a faster clock and then divide internally.

AMCC

 

[OvErFlO]

Re: Xilinx CLKDLL Error

If I have a External clock without a internal clock to sinchronize,where can I connect CLKFB ?


Thanks

 

[zape]

Xilinx CLKDLL Error

CLK0. You must read Xilinx data sheet.

 

[AMCC]

Re: Xilinx CLKDLL Error

Hi,

You should take a look at the Xilinx data Sheet since the DCM is not a trivial logic.

Any way, the DCM tries to put a defined phase between CLKIN and CLKFB. In the most simple form you will have CLK0 connected (throu a clkbuffer) to CLKFB. This means that the output of the DCM will be phase alligned with the clock input.

You can also have CLK2X in this case (that will also be phase alligned with CLKIN).

You can also have an external (other) clock input connected to the CLKFB (typically this is done when you want to have the same phase between the input and output clock OUTSIDE THE chip by bringing the output back again by the CLKFB).

Please not that this is NOT a complete (or even a fair) explanation of the working modes of the DCM.

 

[ashishjindal76]

Xilinx CLKDLL Error

straight away i think that u have to use higher clock sppeds and that would solve that out.

ashish