xilinx bit files - some questions

[Tomby]

xilinx prom + xcs file

Can anyone tell me whether the bit files ise generates for the different modes(i.e. master/slave serial etc. and jtag) is always the same? If it is the same then only the mode pins tell what mode is actually to be used to program the fpga? What if jtag is avaible for all the mode selections such as in spartan xcs chips? Thanks

 

[zcq]

xilinx bitfile jtag.clk to cclk

I dont think they are the same. Just guess!
Hope anybody can confirm it!

 

[ktuluboy]

Re: xilinx bit files

I know for sure that if you connect a JTAG port and try to download a BIT file with it, it will override any of the programming mode selected by the mode pin.

For the difference between the two BIT files....There's a difference between the two of them...and I think it's only one bit in the BIT file (but i'm not so sure about that).

Ktuluboy

 

[ktuluboy]

Oh yeah... I don't remember with Xilinx ISE 4.2...but i know that witht XIlinx ISE 5.1, when you try to program a bit file via JTAG that has been generated to start with the CCLK set as it's starting clock, the software will warn you about it (and i think it ask you to modify the bit file to use the proper starting clock).

ktuluboy

 

[tlp71@hotmail.com]

Re: xilinx bit files

The only difference is for the device or for the architecture, ex prom serial or parallel.
Bye.
G.

 

[Ohh2]

Re: xilinx bit files

For the same design you may have different configuration commands (incl. parameters) in the bitstream. For example, you can specify either using Jtag clock or CCLK.