XC9536 100 MHz Divider

[brunoaduarte]

xc9536

Hi, i have a 100 MHz clock source and want to divide it by 11 to obtain 9.091 MHz and by 22 to obtain 4.54 MHz on different clock outputs, how can i do it ?

module clkdiv(clk,q);
	input clk;
	output q;
	reg [1:0] COUNT;
	initial COUNT=0;
	assign q=COUNT[1];
	always @(posedge clk)
	begin
	  COUNT = COUNT + 1;
	end
endmodule

If i could replace that always statement to something like

always @(posedge clk or negedge clk)

i think it could work, but i can't, i get error

 

[brunoaduarte]

verilog unexpected token

I have this .JED file for programming my XC9536XL, it does divide the 100 mhz clock by 11 and 22, but i need to add some extra circuit on it.

Does any1 knows if it's possible to disassemble it ?

 

[wade_hassler]

xc9536xl clock

Something like:

-module divby_11_22(
- input clk,
- output reg by_11,
- output reg by_22
- );
-reg [4:0] counter;
-always @(posedge clk)
- begin
- if (counter == 5'd21) counter <= 5'd0;
- else counter <= counter + 5'd1;
-
- // divide-by-11 clock is high for 5, low for 6
- if ((counter == 5'd0)||(counter == 5'd11)
- by_11 <= 1'b1;
- if (counter == 5'd5) || (counter == 5'd16))
- by_11 <= 1'b0;
-
- // divide-by-22 is 11 high, 11 low
- if (counter == 5'd0) by_22 <= 1'b1;
- if (counter == 5'd11) by_22 <= 1'b0;
-
- end
-endmodule

Haven't tested this, but it looks workable. This will not quite give you a 50% duty-cycle on the /11 clock, but close.
Wade

 

[brunoaduarte]

clock xc9536xl

Thank's, but it didn't worked the way it's written:

Tried to compile it on Xilinx ISE, verilog module, but got errors:

module divby_11_22(clk, by_11, by_22);
 input clk; 
 output by_11;
 output by_22;
 
reg [4:0] counter; 
always @(posedge clk) 
	begin 
		if (counter == 5'd21) counter <= 5'd0; 
		else counter <= counter + 5'd1; 
			// divide-by-11 clock is high for 5, low for 6 
			if ((counter == 5'd0)||(counter == 5'd11) by_11 <= 1'b1; 
			if (counter == 5'd5) || (counter == 5'd16)) by_11 <= 1'b0; 
					 
			// divide-by-22 is 11 high, 11 low 
			if (counter == 5'd0) by_22 <= 1'b1; 
			if (counter == 5'd11) by_22 <= 1'b0; 
 	end 
endmodule

Here's the synthesis report

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "DIV.v" in library work
ERROR:HDLCompilers:26 - "DIV.v" line 32 unexpected token: 'by_11'
ERROR:HDLCompilers:26 - "DIV.v" line 32 expecting ')', found ';'
ERROR:HDLCompilers:26 - "DIV.v" line 33 unexpected token: '||'
ERROR:HDLCompilers:26 - "DIV.v" line 33 unexpected token: '('
ERROR:HDLCompilers:26 - "DIV.v" line 33 unexpected token: 'counter'
ERROR:HDLCompilers:26 - "DIV.v" line 33 expecting 'end', found '5'
Module <divby_11_22> compiled
ERROR:HDLCompilers:26 - "DIV.v" line 33 expecting 'endmodule', found ''d'
Compiling verilog file "TESTE.vf" in library work
Module <TESTE> compiled
Analysis of file <"TESTE.prj"> failed.

 

[wade_hassler]

hdlcompilers:26

This (modified) copy compiles correctly under Quartus 8

//////////////////////////////////////////////
module test(clk, by_11, by_22);
input clk;
output reg by_11;
output reg by_22;

reg [4:0] counter;
always @(posedge clk)
begin
if (counter == 5'd21) counter <= 5'd0;
else counter <= counter + 5'd1;
// divide-by-11 clock is high for 5, low for 6
if ((counter == 5'd0)||(counter == 5'd11)) by_11 <= 1'b1;
if ((counter == 5'd5) || (counter == 5'd16)) by_11 <= 1'b0;

// divide-by-22 is 11 high, 11 low
if (counter == 5'd0) by_22 <= 1'b1;
if (counter == 5'd11) by_22 <= 1'b0;
end
endmodule
////////////////////////////////////////////////////////////

 

[brunoaduarte]

free codes download for xc9536

Well, now it compiled, but it did not generated the 2 clock outputs on simulation , as you can see on the attached image.

 

[wade_hassler]

xilinx ise unexpected token: to a module

See attachment for the output of the Altera simulation.
I don't know what to say, except that it looks like we have a simulator duel going.
Wade Hassler

 

[brunoaduarte]

divide by 5 counter 100 mhz

I've flashed the XC with the .JED file, it really works... It's generating both 9 MHz and 4 MHz outputs.

Sorry, there must be some problem with my simulator....

Thank you !

 

[nataraja]

i want to know the speed grades of XC9536 in Mhz
all versions are capable of running at high speed ??
and how to see for the speed variation by name ?