If the PLL/VCO approach is optimized for phase noise this should not be the case. What I mean by optimized for phase noise is plot the phase noise of the VCO and the reference on the same graph. Then multiply the reference up to the VCO frequency (in this case add 36 dB). There will be a point where the two curves cross, this is (roughly) where your loop bandwidth should be for optimum phase noise. Then you get the better phase noise of the reference close-in and the better phase noise of the VCO further out.