X errors when running IC5.0 on Linux

[aidans]

Hellow there
I have installed IC5.0 in my Linux box
the license is set properly, but I can not run icfb or icms

the X sever errors are following, can anybody tell me what's going wrong?

Thank you

tar@debian:~$ icfb
X Error of failed request: BadName (named color or font does not exist)
Major opcode of failed request: 45 (X_OpenFont)
Serial number of failed request: 16
Current serial number in output stream: 32


16:09:40 (lmgrd) -----------------------------------------------
16:09:40 (lmgrd) Please Note:
16:09:40 (lmgrd)
16:09:40 (lmgrd) This log is intended for debug purposes only.
16:09:40 (lmgrd) There are many details in licensing policies
16:09:40 (lmgrd) that are not reported in the information logged
16:09:40 (lmgrd) here, so if you use this log file for any kind
16:09:40 (lmgrd) of usage reporting you will generally produce
16:09:40 (lmgrd) incorrect results.
16:09:40 (lmgrd)
16:09:40 (lmgrd) -----------------------------------------------
16:09:40 (lmgrd)
16:09:40 (lmgrd)
16:09:40 (lmgrd) FLEXlm (v8.2a) started on debian (linux) (5/13/2005)
16:09:40 (lmgrd) FLEXlm Copyright 1988-2002, Globetrotter Software, Inc.
16:09:40 (lmgrd) US Patents 5,390,297 and 5,671,412.
16:09:40 (lmgrd) World Wide Web: **broken link removed**
16:09:40 (lmgrd) License file(s): cadenceic5/cadenceic5.dat
16:09:40 (lmgrd) lmgrd tcp-port 5280
16:09:40 (lmgrd) Starting vendor daemons ...
16:09:40 (lmgrd) Started cdslmd (internet tcp_port 32784 pid 2516)
16:09:40 (cdslmd) FLEXlm version 8.2a
16:09:40 (cdslmd) Server started on debian for: 100
16:09:40 (cdslmd) 21900 26000 Affirma_sim_analysis_env
16:09:40 (cdslmd) CWAVES UET VERILOG-XL
16:09:40 (cdslmd) VXL-VCW VXL-VET VXL-VLS
16:09:40 (cdslmd) VXL-VRA 111 11400
16:09:40 (cdslmd) 12141 200 206
16:09:40 (cdslmd) 207 21060 LEAPFROG-CV
16:09:40 (cdslmd) 21400 276 278
16:09:40 (cdslmd) Composer_Spectre_Sim_Solution 283 300
16:09:40 (cdslmd) 3000 Virtuoso_XL 302
16:09:40 (cdslmd) Virtuoso_Schem_Option 305 32100
16:09:40 (cdslmd) OASIS_Simulation_Interface 32120 Artist_Statistic
s
16:09:40 (cdslmd) 32125 Corners_Analysis 32130
16:09:40 (cdslmd) Artist_Optimizer 32140 32150
16:09:40 (cdslmd) 32190 32500 32501
16:09:40 (cdslmd) 32510 32520 SpectreRF
16:09:40 (cdslmd) 32521 Affirma_RF_SPW_model_link 32530
16:09:40 (cdslmd) Affirma_RF_IC_package_modeler 32550 32760
16:09:40 (cdslmd) 33010 33011 Device_Level_Placer
16:09:40 (cdslmd) 33015 Virtuoso_Core_Optimizer 33016
16:09:40 (cdslmd) Virtuoso_Core_Characterizer 33301 34500
16:09:40 (cdslmd) 34510 34511 Substrate_Coupling_Analysis
16:09:40 (cdslmd) 34515 34520 34525
16:09:40 (cdslmd) 34530 Affirma_AMS_distrib_processing 370
16:09:40 (cdslmd) 371 37100 373
16:09:40 (cdslmd) 374 LAS_Cell_Optimization 37500
16:09:40 (cdslmd) Device_Level_Router 41000 501
16:09:40 (cdslmd) 550 570 940
16:09:40 (cdslmd) 945 952 Composer_EDIF300_Connectivity
16:09:40 (cdslmd) 953 Composer_EDIF300_Schematic BTAHVMOS
16:09:40 (cdslmd) Spectre_BTAHVMOS_Models BTASOI Spectre_BTASOI_M
odels
16:09:40 (cdslmd) NTMODELS Spectre_NorTel_Models SpectreBasic
16:09:40 (cdslmd) STMODELS Spectre_ST_Models 11701
16:09:40 (cdslmd) 11702 11703 11710
16:09:40 (cdslmd) DRACSLAVE DRACDIST DRAC2CORE
16:09:40 (cdslmd) 12500 14000 _21900
16:09:40 (cdslmd) 14010 14020 14040
16:09:40 (cdslmd) 14050 EBD_power EBD_edit
16:09:40 (cdslmd) EBD_floorplan ALL_EBD 14060
16:09:40 (cdslmd) Datapath_Preview_Option 14065 Datapath_Verilog
16:09:40 (cdslmd) 14066 Datapath_VHDL 14070
16:09:40 (cdslmd) Preview_Synopsys_Interface 14101 14111
16:09:40 (cdslmd) 14120 14130 14140
16:09:40 (cdslmd) 14300 14400 14410
16:09:40 (cdslmd) 312 314 316
16:09:40 (cdslmd) 318 322 336
16:09:40 (cdslmd) 365 51020 FPGA_Flows
16:09:40 (cdslmd) FPGA_Tools xilEdif xilConceptFE
16:09:40 (cdslmd) xilCds 51021 51022
16:09:40 (cdslmd) xilComposerFE PIC_Utilities 51023
16:09:40 (cdslmd) 51070 51100 51170
16:09:40 (cdslmd) 681 ConcICe_Option 70110
16:09:40 (cdslmd) DRACERC DRAC3DRC Distributed_Dracula_Opti
on
16:09:40 (cdslmd) 70120 DRAC3LVS DRACLVS
16:09:40 (cdslmd) 70130 DRACLPE DRACPRE
16:09:40 (cdslmd) 70510 70520 71110
16:09:40 (cdslmd) Assura_DV_design_rule_checker 71120 Assura_DV_LVS_ch
ecker
16:09:40 (cdslmd) 71130 Assura_DV_parasitic_extractor 71510
16:09:40 (cdslmd) 71520 727 728
16:09:40 (cdslmd) 729 730 DRACPLOT
16:09:40 (cdslmd) 731 DRAC2DRC 733
16:09:40 (cdslmd) DRAC2LVS 761 763
16:09:40 (cdslmd) DRAC3CORE 780 DRACPG_E
16:09:40 (cdslmd) 785 DRACACCESS 792
16:09:40 (cdslmd) 920 950 960
16:09:40 (cdslmd) 963 964 965
16:09:40 (cdslmd) 966 972 974
16:09:40 (cdslmd) 12110 12111 900
16:09:40 (cdslmd) 991 992 994
16:09:40 (cdslmd) 995 tw01 tw02
16:09:40 (cdslmd) 20135 20235 20240
16:09:40 (cdslmd) 21200 252 synSmartLib
16:09:40 (cdslmd) synSmartIF 253 251
16:09:40 (cdslmd) synTiOpt 26400 VERITIME
16:09:40 (cdslmd) 50000 50010 50110
16:09:40 (cdslmd) 50200
16:09:40 (cdslmd)
16:09:40 (cdslmd) All FEATURE lines for this vendor behave like INCREMENT lines
16:09:40 (cdslmd)

 

[yeechyan]

Re: X errors in IC5.0

Cadence will only run in 8bit or 24bit colour mode. Check the colour mode settings and make sure the settings is 24bit colour mode.

 

[arunragavan]

X errors in IC5.0

setenv LD_KERNEL_ASSUME 2.4.1
try this command
fix color mode to true color
may be it will work