writng a file in verilog

[Tajwar]

I ma trying this code for writing a file but cant include data.v file. I have write data file in a doc and saved it as '.v' file but when i add it to stimulus it givess me error

module readmemh_demo;

reg [31:0] Mem [0:11];

`include "data.v"

integer k;
initial begin
#10;
$display("Contents of Mem after reading data file:");
for (k=0; k<6; k=k+1) $display("%d:%h",k,Mem[k]);
end

endmodule

EXAMPLE: data.v file
initial
begin
Mem[0] = 32'h234ac;
Mem[1] = 32'h23ca5;
Mem[2] = 32'hb3c34;
Mem[3] = 32'h23a4a;
Mem[4] = 32'h234ca;
Mem[5] = 32'hb3234;
end

 

[achaleus]

keep all the files in the same folder and in coding where u use the defines, as a first line : `include xyz.v then when simulating it is better to : vlog src/*.v; vsim src/*.v
this is done so that the included file is also compiled along with the design files