Writing timing constraints for clock divider

[Qwerty112233]

Hi,

I am wondering how to write these generated clock constraints at clk out pin, when there is a clk in coming in, div_en and cg en are other signals going to flop and clock gate respectively.

Can i just say
create_generated_clock -source <CLK pin of flop in the picture> -master CLKIN -divide_by N [get_pins CLKOUT]

I need to ask RTL designer what the N value needs to be..