Writing testbenches efficiently ... share your experience.

[afnam]

Hi all,

As for the process of design verification, I thought it would be useful if each one of us briefly demonstrates his/her own experience in building an efficient testbench to validate his/her design...

I only thought of the following items to be considered (of course you may want to consider others):

- Tools used to automatically generate testbench (if any).
- Testbench language used.
- Useful books (if any).
- % time allocated to verification phase (out of total design time).
- Comment and evaluate your experiment.
- What to consider next time.

Hopefully, this thread could become a reference for designers to continually learn about, evaluate, and compare different approaches for design validation.

Thanks for reading,
afnam.

 

[semiconductorman]

Re: Writing testbenches efficiently ... share your experienc

Thought i could add a few more points here ...
# Methodology to be followed -> for example if your design has a processor in it u have the option of either using instruction driven testing ( h/w s/w co-simulation ) or using a bfm for your processor.
# System integration testing (u may choose to either simulate the whole system) or use c , C++ or system C to calculate bootleneck analysis etc
# Depending on how big ur desing is you may need to run a few application driven test cases

 

[radix]

Re: Writing testbenches efficiently ... share your experienc

If you haven't done so already check out:

https://verificationguild.com

for some good, detailed discussions on verification.

Radix