Mar 7, 2013 #1 B blach100 Junior Member level 3 Joined Jul 15, 2011 Messages 30 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,483 hi guys , is writing into a file in VHDL module happening after synthesizing or after simulation?
Mar 8, 2013 #2 Y yourcheers Member level 1 Joined Jul 18, 2008 Messages 33 Helped 8 Reputation 16 Reaction score 8 Trophy points 1,288 Activity points 1,441 In real hardware logic you can't write into any file, writing into file is only simulation option?