Code Verilog - [expand] |
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
| `timescale 1ns / 1ps
module trigger_sync (
input wire clk,
input wire rst_n,
input wire trigger_in,
output reg trigger_out
);
reg trigger_sync_d1;
reg trigger_sync_d2;
reg trigger_edge_detect;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
trigger_sync_d1 <= 1'b0;
trigger_sync_d2 <= 1'b0;
trigger_edge_detect <= 1'b0;
end else begin
trigger_sync_d1 <= trigger_in;
trigger_sync_d2 <= trigger_sync_d1;
trigger_edge_detect <= trigger_sync_d1 & ~trigger_sync_d2;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
trigger_out <= 1'b0;
end else begin
trigger_out <= trigger_edge_detect;
end
end
endmodule |
[Added syntax tags]
Last edited by a moderator: