[SOLVED] Writing a verilog code to generate a single pulse?

[BALU@FPGA]

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Code Verilog - [expand]
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`timescale 1ns / 1ps
 
module trigger_sync (
    input wire clk,
    input wire rst_n,
    input wire trigger_in,
    output reg trigger_out
);
 
    reg trigger_sync_d1;
    reg trigger_sync_d2;
    reg trigger_edge_detect;
 
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            trigger_sync_d1 <= 1'b0;
            trigger_sync_d2 <= 1'b0;
            trigger_edge_detect <= 1'b0;
        end else begin
            trigger_sync_d1 <= trigger_in;
            trigger_sync_d2 <= trigger_sync_d1;
            trigger_edge_detect <= trigger_sync_d1 & ~trigger_sync_d2;
        end
    end
 
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            trigger_out <= 1'b0;
        end else begin
            trigger_out <= trigger_edge_detect;
        end
    end
 
endmodule

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