Write response of axi

[vir_1602]

Hi all
can anybody Tell me is write response be always on next clock edge of Wlast signal or there can be delay between wlast and Write response.

as far as I have read it is like bresponse is always at the next clock edge of Wlast (i.e when Wlast beat is acknowledged by wready).

Thanks in adv
Vir_1602

 

[harerama]

Hi,
I go through spec may be available all the details or arm web site for information.

 

[vir_1602]

I have gone through the spec and there is only one line written about it that is "Write response must always follow the last write transfer" and I have also gone through many other sites. all the time I have come on to the above conclusion but still it is not clearly written

Thanks and regards
Vir_1602

 

[sameer_dlh25]

Hi Vir_1602,

"write response be always on next clock edge of Wlast signal or there can be delay between wlast and Write response."

It is definitely possible have delay between WLAST and write response.Please note that if write response has to be given always in next cycle of WLAST then there is no need of BVALID.

Only mentioned limitation in protocol is that in any case write response can not occur before WLAST (last data beat).

I hope this help.

Cheers
Sameer

 

[vir_1602]

hi Sammeer

Thanks ; ur reply is really useful.

Thanks and regards
virat sharma