[SOLVED] Write data into file fail

Hi all,

I have an issue..I am implementing dilation filter for my image processing project on an fpga..I have written the code and trying to simulate and check the performance.
2 days back my data was being written into the file but now my data file is empty.
Can you kindly tell me what do i need to do??

My partial code is---

library IEEE;library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use STD.textio.all;
use std.env.all;

entity testbench is
end testbench;

architecture Behavioral of testbench is

file data:text open write_mode is "data.txt";

COMPONENT blk_mem2
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

-- signal declarations for bram_test.
signal ena : std_logic := '1';
signal wea : std_logic_vector(0 downto 0) := "0";
signal dina : std_logic_VECTOR(7 downto 0) := "UUUUUUUU";
signal douta : std_logic_VECTOR(7 downto 0) := "UUUUUUUU";
signal addra : std_logic_VECTOR(11 downto 0):= "000000000000";
signal clk : std_logic;

begin

--Instantiating BRAM.
bram : blk_mem2
port map(
clka => clk,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);

--Simulation process.
bram1 : process(clk)
-------------
-------------
.
.
.
.
.
-------------
variable txt:line;
begin
if (rising_edge(clk))
-------------
-------------
.
.
.
.
.
-------------
wea <= "1";
dina<=temp1;
if(falling_edge(clk)) then
write (txt,temp1);
writeline(data,txt);
end if;
end process bram1;

--Clock generation

process
begin
clk <= '1';
wait for 1ns; --"ON" time.
clk <= '0';
wait for 1ns; --"OFF" time.
end process;

end Behavioral;

I also started a new project in xilinx ise and tried the simulation but my data file was still empty.Can you guys tell me what the resaon is?

Thanks,
Sreeni

sreevenkjan said:

Hi all,

I have an issue..I am implementing dilation filter for my image processing project on an fpga..I have written the code and trying to simulate and check the performance.
2 days back my data was being written into the file but now my data file is empty.
Can you kindly tell me what do i need to do??

My partial code is---

library IEEE;library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use STD.textio.all;
use std.env.all;

entity testbench is
end testbench;

architecture Behavioral of testbench is

file data:text open write_mode is "data.txt";

COMPONENT blk_mem2
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

-- signal declarations for bram_test.
signal ena : std_logic := '1';
signal wea : std_logic_vector(0 downto 0) := "0";
signal dina : std_logic_VECTOR(7 downto 0) := "UUUUUUUU";
signal douta : std_logic_VECTOR(7 downto 0) := "UUUUUUUU";
signal addra : std_logic_VECTOR(11 downto 0):= "000000000000";
signal clk : std_logic;

begin

--Instantiating BRAM.
bram : blk_mem2
port map(
clka => clk,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);

--Simulation process.
bram1 : process(clk)
-------------
-------------
.
.
.
.
.
-------------
variable txt:line;
begin
if (rising_edge(clk))
-------------
-------------
.
.
.
.
.
-------------
wea <= "1";
dina<=temp1;
if(falling_edge(clk)) then
write (txt,temp1);
writeline(data,txt);
end if;
end process bram1;

--Clock generation

process
begin
clk <= '1';
wait for 1ns; --"ON" time.
clk <= '0';
wait for 1ns; --"OFF" time.
end process;

end Behavioral;

I also started a new project in xilinx ise and tried the simulation but my data file was still empty.Can you guys tell me what the resaon is?

Thanks,
Sreeni

Click to expand...

i don't see file_open, file_close, actually filw writing seems infinite, no ending to write.. from what i understand...

Please show all the code.

Hi TrickyDicky

my code is

library IEEE;library std;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
--use std.env.all;

entity testbench is
end testbench;

architecture Behavioral of testbench is

COMPONENT blk_mem2
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ena : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

--inputorary signal declarations for bram_test.
signal ena : std_logic := '1';
signal wea : std_logic_vector(0 downto 0) := "0";
signal dina : std_logic_VECTOR(7 downto 0);
signal douta : std_logic_VECTOR(7 downto 0);
signal addra : std_logic_VECTOR(11 downto 0):= "000000000000";
signal clk : std_logic;

begin

--Instantiating BRAM.
bram : blk_mem2
port map(
clka => clk,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);

--Simulation process.
bram1 : process(clk)
variable temp,temp1 : std_logic_vector(7 downto 0);
variable count,dil,depth : integer := 0;
variable carry : std_logic := '0';
variable carry_fwd : std_logic := '0';
file data:text open write_mode is "data.txt";
variable txt:line;
begin
--wait for 2 ns;
--addra <= "0000"; --reset the address value for reading from memory location "0" reading all the memory locations in the BRAM.
if(rising_edge(clk)) then
ena <= '1';
wea <= "0";
addra <= "000000000000";
dina <= "00000000";
for dil in 0 to 3 loop
for depth in 0 to 2177 loop
--ena <= '1';
--wea <= "0";
--temp := douta;
--wea <= "0";
--report "finished pass1";
--wait for 4ns;
carry := carry_fwd;
for count in 0 to 7 loop
temp := douta;
if (temp(count) = '0' and carry = '0') then
temp1(count) := '0';
carry := '0';
--carry_fwd := '0';
elsif (temp(count) = '0' and carry = '1') then
temp1(count) := '1';
carry := '0';
--carry_fwd := '0';
elsif (temp(count) = '1' and carry = '0') then
--carry_fwd := '1';
if (count = 0) then
temp1(count) := '1';
carry := '1';
else
temp1(count-1) := '1';
temp1(count) := '1';
carry := '1';
end if;
elsif (temp(count) = '1' and carry = '1') then
if (count = 0) then
temp1(count) := '1';
carry := '1';
else
temp1(count-1) := '1';
temp1(count) := '1';
carry := '1';
end if;
end if;
if (count = 7 and carry = '1') then
carry_fwd := '1';
end if;
--wait;
end loop;
wea <= "1";
dina <= temp1;
-- if (addra = "1001") then
-- addra <= "0000";
-- end if;
wea <="0";
addra <= addra + "1";
if (addra = "100010000001") then
addra <= "000000000000";
end if;
end loop;
report " Number of loops completed = "& integer'image(dil);
--wait;
-- if (dil = 3 and depth = 8) then
-- --ena <= '0';
-- --report "Simulation Finished";
-- finish(0);
-- end if;
end loop;
-- if (dil = 3 and depth = 2177 and addra = "100010000001") then
-- --ena <= '0';
-- --report "Simulation Finished";
-- finish(0);
-- end if;
if(falling_edge(clk)) then
write (txt,temp1);
writeline(data,txt);
end if;
end if;
end process bram1;

--Clock generation - Generates 500 MHz clock with 50% duty cycle.

process
begin
clk <= '1';
wait for 1ns; --"ON" time.
clk <= '0';
wait for 1ns; --"OFF" time.
end process;

end Behavioral;

Can you tell me where my error is??

regards,
Sreeni

Because you have the write statements inside an "if falling_edge(Clk)" clause, but that is inside an "if rising_edge(clk)" clause. It cannot rise and fall at the same time.

- - - Updated - - -

PS. even though your dil loop goes around 100s of times, the address only increments by 1 ALL of the loops.

The proble is solved thanks a lot!!

- - - Updated - - -

hi Tricky dicky what do u mean by the last line..I did not understand.
I am not able to stop the simulation through my code..However I am able to stop it by defining the time resolution in the isim..is it possible to give a time resolution value in my test bench??

No you cannot give a time resolution. But its because you have assigned the signal inside a loop. Because the process never suspends, the signals dont get updated between loop iterations. It will just take the last value assigned to it.

- - - Updated - - -

As an example:


After reset, the addr signal will increase by 1 on each rising edge of the clock, not by 21. Addrv will increase by 21 on each clock edge, as its a variable.