Write code for UART for begginer

[rkmanju]

Hi everybody,
I am a biginner for the VHDL Design, as a beginner i wants to write code for UART, can somebody help me out.


Thanks

 

[hafeez]

What kind of Help u need? do u need codes for UART?

 

[rkmanju]

What kind of Help u need? do u need codes for UART?

just i want the code for UART( for both Tx and Rx)

 

[Electro_Nic]

Hi,

here is a good thread for it.. RS232 VHDL-core | Comp.Arch.FPGA | FPGARelated.com
maybe interesting.. i used it to do a part of my own UART

 

[pratchaya.aut]

i will think first then tell you later

 

[hafeez]

I am posting code for Transmitter section, i have written his in hurry, dnt find time.
Will post reciever code soon, This code accepts 8-bit data from user, and sends to PC with the baud rate depending on Clock speed. Tested!

library ieee;
use ieee.std_logic_1164.all;

entity serial is
port
(txd: out std_logic;
clk:in std_logic;
enable: in std_logic;
data:in std_logic_vector(7 downto 0));
end serial;

architecture beh of serial is
type state is (idle,start,d0,d1,d2,d3,d4,d5,d6,d7,stop);
signal pr_stat,nxt_stat:state;
signal temp: std_logic;
begin
process(enable,clk)
begin
if (enable='0') then
pr_stat <= idle;
elsif (clk'event and clk='1') then
pr_stat <= nxt_stat;
txd <= temp;
end if;
end process;

process(data,pr_stat)
begin
case pr_stat is
when idle =>
temp <= '1';
nxt_stat <= start;
when start =>
temp <= '0';
nxt_stat <= d0;
when d0 =>
temp <= data(0);
nxt_stat <= d1;
when d1 =>
temp <= data(1);
nxt_stat <= d2;
when d2 =>
temp <= data(2);
nxt_stat <= d3;
when d3 =>
temp <= data(3);
nxt_stat <= d4;
when d4 =>
temp <= data(4);
nxt_stat <= d5;
when d5 =>
temp <= data(5);
nxt_stat <= d6;
when d6 =>
temp <= data(6);
nxt_stat <= d7;
when d7 =>
temp <= data(7);
nxt_stat <= stop;
when stop =>
temp <= '1';
nxt_stat <= idle;
end case;
end process;

end beh;