Write and read operations for SRAM using PSPICE

rajrevanth61 · Mar 24, 2014

Hello EVERYONE,

I have written the basic pspice netlist for 6T SRAM, Now i want to perform the read and write operations on it. Should I need to incorporate that logic in the basic netlist only or should i write another netlist for read and write and then relate the basic netlist with the read and write netlist. Please help me.

here is my netlist for sram

*sram*

*source
vdd vdd 0 dc 2

*access control
vwl wl 0 pulse(0 4 0 100u 100u 2m 8m)

*data control
vbl bl 0 dc 1
vblb blb 0 pulse(0 1 5m 100u 100u 2m 8m)

*transistors used for latching
m1 Q QR 0 0 NMOS l=1u w=0.35u

m2 Q QR vdd vdd PMOS l=1u w=0.70u

m3 QR Q 0 0 NMOS l=1u w=0.35u

m4 QR Q vdd vdd PMOS l=1u w=0.70u

*transistors used for data access
m5 bl wl QR QR NMOS l=1u w=0.35u
m6 blb wl Q Q NMOS l=1u w=0.35u

.model NMOS NMOS [kp=20u vto=0 lambda=0]
.model PMOS PMOS [kp=20u vto=0 lambda=0]

.end

atripathi · Mar 30, 2014

Either of suggested method would work. Keeping these two as separate netlist and using them together is recommended option. This approach would provide you flexibility to reuse these two in other circuits as well.

rajrevanth61 · May 30, 2014

Now I have two separate netlists for Read and write operation of SRAM, how do i combine them?

Write and read operations for SRAM using PSPICE

rajrevanth61

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atripathi

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rajrevanth61

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Write and read operations for SRAM using PSPICE

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