wrap your minds around this one.. HDL design

I am trying to make a asyncronous edge detect which sets a reg until the negedge of a different signal clears that reg. No clock. I've been working at it for 8 hours now.. best i've gotten is detecting a edge, but a second edge kills cancels each other out if the detection reg isn't cleared first.. does anyone have any ideas? Perferably in verilog..

jelydonut

hope this helps (by the way, in verilog x-> 1 or x->0 is an edge).

module ex1(in,reset_b,out);
input in,reset_b;
output out;
reg out;
always @(in or negedge reset_b)
if (!reset_b) out<=1'b0;
else out<=~out;

endmodule



module testbench ;
reg IN1 , RESET ;
wire OUT;
initial
$monitor( $time , " OUT = %b , IN1 = %b , RESET = %b " ,OUT , IN1 , RESET );
initial
begin

RESET=1'b0; // reset, initial value
#10 IN1=1'b0;RESET=1'b1;
#10 IN1=1'b1;
#5 RESET=1'b1;
#10 RESET=1'b0;IN1=1'b0;
#10 RESET = 1'b1;IN1=1'b1;

end

ex1 ex11(IN1 , RESET, OUT );

endmodule

Thanks, but that won't work.. atleast not as i worded it..

it could be done say.. on the negedge of read to temporary store the current state into a reg.. then do a ^ in a assign to detect the change. With a always statement to set the bit.. but then the issue comes up.. what if the delta occurs during the store of the current state for compairson in the assign? You could miss that delta all together.. so then you could say.. ok.. i'll store it to a different reg on the posedge and try to use that as a compairson to the negedge to check if a transition happened during the read.. next thing you know you have non working code.. or code that works, but won't synthesize.. If i could garrentee that the clock would be a minimum frequency always then i could just synchronize the input to the clock and all would be fixed..

jelydonut

Pls post your trial code to avoid go in the same way you had done. I hop it is in VHDL to help