You can expect that the performance spread over process corners is similar to +-3sigma process MC spread if your circuit is a standard logic gate. That's because the speed of logic depends on maximum Idsat and the process corners were created to show the extreme values of Idsat.
Whereas if your circuit performance depends on analog small signal parameters such as rds, Cgs, ... then you may see a large difference between process MC and process corner run.
Secondly, process corners do not contain correlation information. You can mix corners of resistors, BJT and MOS at will; but many of these mixed corner combinations are physically impossible and useless to simulate. Process MC instead allows to correlate devices. So, if your circuit contains HVT and LVT MOS and/or moscaps, then again process corner run and process MC run may return very different results.
This is not related to local MC (mismatch MC). You can mix local MC with process corner, or can mix local MC with process MC.