wondering how to make the simulation work with error Error: (vsim-3174)

Code VHDL - [expand]
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USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
 
PACKAGE config_pack IS
 
 
    CONSTANT config_clock_period : time   := 1000 ns; -- period of clock as one micro second
    CONSTANT config_post_cycles  : integer := 100; -- idle cycles waiting for new potential new config commands
    CONSTANT post_command_delay  : time    := config_clock_period * config_post_cycles;
 
 
----potential config commands with 3 bits------
    ALIAS slv IS std_logic_vector;
 
    CONSTANT off             : slv(2 DOWNTO 0) := "000"; --pulse generator is inactivated
    CONSTANT vol_m           : slv(2 DOWNTO 0) := "001"; --programmed to voltage mode
    CONSTANT cur_m           : slv(2 DOWNTO 0) := "010"; --programmed to current mode
  CONSTANT vdd             : slv(2 DOWNTO 0) := "011"; --pull the output to VDD
    CONSTANT charge_balance  : slv(2 DOWNTO 0) := "100"; --maybe need to be charge balance
    CONSTANT gnd             : slv(2 DOWNTO 0) := "111"; --maybe gnd
    ----------------------------------------------------------------------
    TYPE STATE_T IS (PNEG, PPOS, PSHT, PINT);
  
  CONSTANT TN : INTEGER;         --NEGATIVE PHASE WIDTH
  CONSTANT TP : INTEGER;         --POSITIVE PHASE WIDTH
  CONSTANT TI : INTEGER;         --INTERMEDIATE PHASE WIDTH
  CONSTANT TS : INTEGER;         --SHORTING PHASE WIDTHx
  CONSTANT PULSE_N : STD_LOGIC_VECTOR(1 DOWNTO 0):="10";
  CONSTANT PULSE_P : STD_LOGIC_VECTOR(1 DOWNTO 0):="01";
  CONSTANT PULSE_S : STD_LOGIC_VECTOR(1 DOWNTO 0):="11";
  CONSTANT PULSE_Z : STD_LOGIC_VECTOR(1 DOWNTO 0):="00";
 
END;
 
 
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE WORK.PROJECT_PACK.ALL;
USE WORK.CONFIG_PACK.ALL;
 
ENTITY FSM_PULSE IS
  PORT(
    CLK, RESET  : IN STD_LOGIC;
    CONFIG      : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    start       : IN STD_LOGIC;
    Pulse       : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
  );
END FSM_PULSE;
 
ARCHITECTURE FSM_BEHAV OF FSM_PULSE IS
  SIGNAL STATE, STATE_N : STATE_T;
  SIGNAL COUNTER : INTEGER RANGE 0 TO (TN+TP+TI+TS);
  SIGNAL PULSE1  : STD_LOGIC_VECTOR(1 DOWNTO 0);
  BEGIN
               
  S_PROC: PROCESS(STATE, STATE_N, COUNTER)
  BEGIN
    STATE_N <= STATE;
    CASE STATE IS 
    WHEN PPOS =>
      PULSE1 <= PULSE_P;
      IF (COUNTER = TP) THEN
        STATE_N <= PINT;
      END IF;
    WHEN PINT =>
      PULSE1 <= PULSE_Z;
      IF (COUNTER = TP + TI)THEN
        STATE_N <= PNEG;
      END IF;
    WHEN PNEG =>
      PULSE1 <= PULSE_N;
      IF (COUNTER = TP + TI + TN)THEN
        STATE_N <= PSHT;
      END IF;
    WHEN PSHT =>
      PULSE1 <= PULSE_S;
      IF (COUNTER = TP + TI + TN+ TS)THEN
        STATE_N <= PPOS;
      END IF;
    WHEN OTHERS => NULL;
    END CASE;
 -------------------------OUTPUT THE PULSE ONLY IF IT IS ENABLED-----------------------   
    IF START='1' THEN
      PULSE <= PULSE1;
    END IF;
    
  END PROCESS S_PROC;
    
  C_PROC: PROCESS
  BEGIN
    WAIT UNTIL CLK'EVENT AND CLK='1';
    STATE <= STATE_N;
    
    IF RESET = '1' THEN
      STATE <= PPOS;
      COUNTER <= 0;
    END IF;
    
    COUNTER <= COUNTER + 1;
  END PROCESS C_PROC;
    
END ARCHITECTURE FSM_BEHAV;

Code VHDL - [expand]
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.project_pack.all;
USE std.textio.ALL;
USE WORK.CONFIG_PACK.ALL;
 
ENTITY FSM_testbench IS
END FSM_testbench;
 
ARCHITECTURE behav OF fsm_testbench IS
   
   -- FSM_PULSE 
    SIGNAL CLK_I         :  STD_LOGIC;
    SIGNAL RESET_I       :  STD_LOGIC;
    SIGNAL CONFIG_I      :  STD_LOGIC_VECTOR(2 DOWNTO 0);
    SIGNAL start_I       :  STD_LOGIC;
    SIGNAL Pulse_I       :  STD_LOGIC_VECTOR(1 DOWNTO 0);
   
   -- needed as parameters for run_command_file but not
   -- used since it is called with ram_mode_v=model
   SIGNAL cycle_init, cycle_done : STD_LOGIC;  -- dummy signals
 
   SIGNAL trace_commands: boolean := false;
 
BEGIN
   FSM1: ENTITY WORK.FSM_PULSE
   PORT MAP(
     CLK        => CLK_I, 
     RESET      => RESET_I,
    CONFIG      => CONFIG_I,
    start       => START_I,
    Pulse       => PULSE_I
   );
 
   P_RST_CLK: PROCESS
      -- generate reset_i & clk_i
      BEGIN
        -- first ten cycles with reset '1'
        reset_i <= '1';
        clk_i <= '0';
        FOR n in 0 TO 9 LOOP
          WAIT FOR config_clock_period / 2;
          clk_i <= '1';
          WAIT FOR config_clock_period / 2;
          clk_i <='0';
        END LOOP;
          reset_i <= '0';
        -- now generate continuous clock with reset '0'
        WHILE TRUE LOOP
           clk_i <= '0';
           WAIT FOR config_clock_period / 2;
           clk_i <= '1';
           WAIT FOR config_clock_period / 2;
        END LOOP;
      END PROCESS P_RST_CLK;
END behav;