without wire load model

That's the command read_lib, but since you do not have a license for that you cannot compile it. A WLM is normally required for synthesis, however, for unit delay type analysis a ZWLM (zero wireload model) is used. You need to contact your library vendor.

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Post19 Feb 2008 20:04 without wire load model Reply with quote
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To do synthesis without WLM you need to create a WLM within your .lib with zero capacitance and zero resistance, or you can create it separately and load it as a .lib.

ASIC_intl said:

Hello
I want to do synthesys without a wireload model and want to do timing report (report_timing) without wire load model. Do any body has any idea to do the synthesys and report_timing without wire load model.

Thanking,
ASIC

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why do you want to compile design without using WLM?

Hi TOMPAUL

I want to see the timing of my design without the effects of interconnect delays. That is I want to know the timing with R=C-0 for all the interconnects in my design.

Now my .db library has a default wire load model. So even if I set R=C=O for all the interconnects using some dc commands io very case while doing report_timing I find the Design compiler to pick up the default wire load model to report the timing (through report_timing command) of the design.

Thanks

Hi ASIC_intl,
You can use set_annotated_delay to annotate zero to all your interconnect nets in your design. When report_timing, DC will only consider non-zero cell delay.

You can do synthesis without a wire load model, only that you would need to be more consevative while giving your timing constraints. That can be done either by giving a lower value of clock period or a higher value of clock uncertainty. In all this, it is assumed that post layout sdf will be used for back annotation at a later stage. So as a first step or in some cases inevitable we use DC to compile the design without a wireload model.

ASIC_intl said:

Hello
I want to do synthesys without a wireload model and want to do timing report (report_timing) without wire load model. Do any body has any idea to do the synthesys and report_timing without wire load model.

Thanking,
ASIC

Click to expand...