matrixofdynamism
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SystemVerilog possesses some very powerful features like assertion based testing and constrained random testing, not to mention OOP. I am sure that people can come up with various ways to create testbenches using all the tools available within SystemVerilog.
Why then have people developed things like VMM, OVM, UVM?
How would you describe UVM? I do know that it stands for universal verification methodology. Besides this it has now become the main industry standard having replaced all other ones like OVM, VMM e.t.c which have all become obsolete. I know that it provides instructions on a certain way to create the test environment when using SystemVerilog for verification. But why do we even need it to begin with?
Why then have people developed things like VMM, OVM, UVM?
How would you describe UVM? I do know that it stands for universal verification methodology. Besides this it has now become the main industry standard having replaced all other ones like OVM, VMM e.t.c which have all become obsolete. I know that it provides instructions on a certain way to create the test environment when using SystemVerilog for verification. But why do we even need it to begin with?