with and without Semicolon at the end of delay statement in Verilog

imbichie · Apr 18, 2013

Hi All,

What is the difference between a without putting a semicolon at the end of @ (posedge spit_clk) and with a semicolon at the end of @ (posedge spit_clk), in the below task.

Means how it will affects the below if condition.

Code:

task Write_End;
    begin
        [B]@ (posedge spit_clk)[/B]
        if (spit_pready == 1'b1) 
        begin
            spit_psel    = 1'b0;   
            spit_penable = 1'b0;
            spit_pwrite  = 1'b0;
        end
    end
endtask

Code:

task Write_End;
    begin
        [B]@ (posedge spit_clk)[COLOR="#FF0000"];[/COLOR][/B]
        if (spit_pready == 1'b1) 
        begin
            spit_psel    = 1'b0;   
            spit_penable = 1'b0;
            spit_pwrite  = 1'b0;
        end
    end
endtask

also what is the difference between #20 and #20; and how it will affects the below statements

FvM · Apr 18, 2013

The semicolon closes the always block, an always block that doesn't enclose other instructions is meaningless.

dave_59 · Apr 18, 2013

What FvM said is gibberish.

Any procedural statement can be proceeded by one or more delay controls @(...) or timing controls #nnn. So

#20 @(posedge clk) A = A + 1;

could also be written as

#20; @(posedge clk); A = A + 1;

This assumes you are inside a begin/end block where the statements are executed serially. You can think of it as

#20 null_statement ; @(posedge clk) null_statement; A = A + 1;

You need to be careful how statements are grouped where only single statements are allowed. For example if you had

Code:

begin
  A = expr1;
  if (A ==5 ) #20; B = expr2;
  C = expr3;
end

The semicolon adter #20 creates two separate statements, and the B = expr2 is now unconditionally executed.

mrflibble · Apr 18, 2013

#20 means "wait 20 time units before proceeding to execute the immediately following statement".

#20; means "wait 20 time units before proceeding to execute the immediately following statement, and oh BTW the immediately following statement is the empty statement".

"Empty statement?!? O_O" you ask? Yes.

Code:

always @(posedge clk) begin
;
;
;
;
end

There we go, 4 empty statements. Doesn't do all that much, but totally legit code.

So #20; effectively just waits 20 time units.

- - - Updated - - -

Repeat after me: refresh page before posting. refresh page before posting... Doh!

I see you already answered it.

imbichie · Apr 19, 2013

Thanks to all for replying,

Now i understand the concept.

with and without Semicolon at the end of delay statement in Verilog

imbichie

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FvM

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dave_59

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imbichie

FvM

mrflibble

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imbichie

imbichie

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with and without Semicolon at the end of delay statement in Verilog

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