You are using blocking assignments in a edge sensitive always block (i.e. to describe FFs), this is not recommended. Blocking assignments do not necessarily describe registers if the code uses the LHS output values on the RHS. In your case using blocking assignments shouldn't affect the results, but is a bad habit to get into as you will eventually write code that does not synthesized the same as it simulates. I advise you to read up on blocking vs. non-blocking assignments.
Thanks for the advice. I changed my actual code and used non-blocking assignments to clear the registers in the else statement.
I can't use non-blocking in the (if) part because I need it to execute sequentially.
I have this for loop in my actual code in the if part to initialize SR_temp, is this OK ? i don't know another way to initialize it except that... and I think I can't use non-blocking assignment in it!
Code:
for (ii = 0; ii <= W/2-2; ii = ii +1 )
begin
{C,SR_temp[i*W +: W]} = SR_temp[i*W +: W] + A[i*W] * (B[2*ii +: 2]<<(2*ii)) + C;
end
another thing, is the use of non-blocking assignment will affect the CLK? i.e make it faster ?!
$display isn't a synthesizable,
Yes, I'm just using it in tracing the code.
tasks are normally not something you would use in synthesizable code, functions yes, but only a much smaller subset of tasks can be synthesized (ones that behave just like a function), this one can be (disregarding the $display) as it contains no timing control statements (and could have been written as a function).
I'm using tasks because the paper I'm working on describes the operations done as a task, so I thought they have used tasks in implementation, Should I change it to a function?
The code looks like someone who has experience writing software trying to apply how you break down problems in software to Verilog. You don't seem to be approaching Verilog from a hardware perspective, where you think of a digital circuit and describe that circuit using Verilog.
Yes, indeed. I have a problem with that. :-(
In Verilog using for loops is just a means to replicate logic in a simple way without writing 100's of lines of unreadable code.
hmmmmmm do you mean when I used for loop to clear registers ??. Is this the correct way??
Case in point is the use of a task to AND each bit makes no sense, the only time I can see working on individual bits makes sense is if the incoming data is serial. To do so with data that arrives as parallel data results in removing any benefit of using a higher level of abstraction to describe the circuit. You might as well write the code using instantiated AND gates. I'm wondering if the same issues apply to your actual design.
Yes you are right, but AND is just an example, I put it in a task to show you that I'm using tasks in my actual code.
In my actual code, each CLK, I read a word of the numbers stored in a memory and manipulating the whole word in the task.
The reason of dividing the numbers into words is to make a scalable design that could be applied to any size numbers. Actually the whole numbers should be stored in a memory and read out word by word. My design should have inputs of W-bit size to store the read numbers, but I didn't know how to link the design with a memory except the way I'm doing (by using 2D array). Perhaps you could advice me with that, and if you have some code examples or tutorials I'll appreciate it.
regarding the warning
FF/Latch < > (without init value) has a constant value of 0 in block < >. This FF/Latch will be trimmed during the optimization process.
What do you think is the reason -based on the code I attached previously- ?
Thanks for your help, really I appreciate it.