wireload model and zero wireload model

[vlsitechnology]

Can anyone explain me the exact phenomena of wireload model or some documents ??

When we are placing the std cells also the tool will calculate the delays through wireload models??
and why do we need to do sanity check like zero rc check ?? why so ?? in backend?
what is the difference between wireload model and zero wireload model

reply me
bye take care

 

[lakshman.ar]

When we are placing the std cells also the tool will calculate the delays through wireload models??
Sol: yes while placing the std cells, the tool calculates the delays of the "nets" from the wireload models and the delay of the "cells" from the .SDF file ( output from ur synth/Timing tool )

Can anyone explain me the exact phenomena of wireload model or some documents ??
sol: Be a bit more specific on what u want ?
what do u mean by phenomena of wire load models ???

 

[vlsitechnology]

I need some material on wireload model can anyone provide?

Added after 5 minutes:

u mean to say the sdf file will also be given for the backend people But i don't think there is an sdf file at the time of placement if it is there then y we are uable to see the sdf file?....so how the tool calculates delay from the sdf file??

 

[lakshman.ar]

once the constraints for the synth are given. ur design will be mapped to the target lib , corect ?
then when this mapping is done, ur netlist will contain the cells tht are frm target lib ( target lib will contain "delaqy" info if the cells being used),
now the synth tool will giv out a .sdf file which contains the delay info of the "cells" only, hence this info can be used during the placement 'if required'.

regarding the info on the WLM : i ll upload some mat bt tmrw morning !!!

 

[vlsitechnology]

Thanks but plz send me sme good stuffs on that
bye take care