[SOLVED] Will SVA be normally ignored by synthesis tools?

Status
Not open for further replies.
L

layowblue

Advanced Member level 4
Joined
Mar 21, 2014
Messages
115
Helped
19
Reputation
38
Reaction score
18
Trophy points
18
Visit site
Activity points
791
Hi all

I thought SVA would be automatically identified and ignored by synthesis tools, but today I got a mail from the synthesis guy saying the SVA lines broke synthesis flow.(The synthesis tool is RTL Compiler)
I did fix it by putting some macro definition to filter out those SVA lines in the RTL.
But I'm still curious about why RC is doing this.
1) Does anyone know if DC would do the same, namely reporting synthesis error upon SVA lines?
2) Are there some settings insdie RC/DC to ignore SVA lines without having to mask them from the synthesis scope?
3) Is there any golden reference from IEEE 1364-2001 saying anything about the SVA VS synthesis?

Thanks a lot
Leo
 

There is no standard from IEEE that specifies which constructs should be synthesizable, or which constructs should be ignored in SystemVerilog. That is up to each synthesis vendor. DC ignores them.
 

Thanks Dave for the quick reply.
Do you know of any possible parameter setting in RTL Compiler that can be used to ignore those SVA lines?
 

Actually, it turns out to be that the guy was not doing synthesis, he was using a CDC tool that complains about the SVA lines.
I tried myself to synthesis SVA-embedded RTL using RC, and there is NO problem for it.

Thanks Dave again for the care.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…