Will Specman die for Vera as Borland die for Micro$oft?

[sweesw]

which training specman developer or user

If not, give me the reason.
I have spent more than 2 weeks on specman and I was wondering why I am still studying this it the language will die anyway?

The ideas of HVL are the same:

1. Contrained Random Stimulus Generation
2. Coverage Support
3. Temporal Assertion
4. Data Packing and Checking

The following two features are not HVL feature but will be necessary with HVL based testbench development tools.

5. Multilanguage Support(Verilog, VHDL, System C)
6. Multisimulator Supoort(NC/XL, VCS-MX, Modelsim)

 

[mami_hacky]

I think specman, is much more difficult to learn than vera.

 

[yeewang]

they'll both die, because of the emerging SystemC/SystemVerilog.
Especially SystemC is actually free of charge to run simulation.

 

[the_penetrator]

SystemC is immature (and buggy that is), SystemVerilog not supported by no tool in the industry (yet...) Expecting Synopsys to release new version supporting SystemVerilog.

the_penetrator©

 

[thriller_wu]

But I think specman will beat vera. Vera is tooooo
slow.

 

[jimjim2k]

SystemC is immature (and buggy that is), SystemVerilog not supported by no tool in the industry (yet...) Expecting Synopsys to release new version supporting SystemVerilog.

the_penetrator©

Modelsim 5.8c from MTI is now supports systemverilog too.

ModelSim's implementation of SystemVerilog is driven by the stability of the spec and customer demand. SystemVerilog has evolved through 2 revisions. Version 3.0 was approved by the Accellera* board at the 2002 Digital Automation Conference. This version is based on the synthesizable subset of Superlog donated by CoDesign and targets modeling. Version 3.1 is an extension of 3.0 with additional constructs that target design verification. Version 3.1 has also been approved by the Accellera board, at the 2003 Design Automation Conference.


tnx

 

[rx300]

After sitting through 3 SystemVerilog seminars hosted by Synopsys FAE, I have to say I'm a bit disappointed. Really, there is not much there that can be compete with what the current HVL can offer. It almost looks like that the folks pushing SystemVerilog have simply "stole" a lot of ideas from VHDL.
Vera is dying. That's for sure.
The problem with Specman is the long learning curve. If there is no Specman expert on your team, I suggest you either find one or you may ask for a few month extra time in your schedule. Once you see the code written by Specman experts, you will find out that there is a lot of things that are so useful but no covered in the 3-day training they offer.
Will Specman ever die? Maybe, but not in the next 5 years.

 

[bigrice911]

OK, man, I think your title shoud be changed to: Will Vera die for Specman as Borland die for Micro$oft. Vera is dying......anyway

 

[rx300]

OK, man, I think your title shoud be changed to: Will Vera die for Specman as Borland die for Micro$oft. Vera is dying......anyway

Vera is dead. Synopsys killed it with their push of SystemVerilog. Tech support is still available, but I heard there is no more development effort.

 

[xworld2008]

specman is very power but hard to study

 

[efundas]

Do we always have to just keep updating ourselves with new langauges, will there be a stable and standard language ever.

 

[zwj_seu]

I'm using specman to verify,and I think is powerful.
All of it's generation ,coverage and check are powerful.
And it's service is good!