Re: Groud Plane capacitance
Well, I dont see any strong reason for the ground layer and the adjacent layer's interlayer capacitance to delay the digital signal output from the TTL gate pin.
As long as the pcb stack is correctly designed and impedance properly controlled and the critial lengths not exceeded, the signal delays will be well within the threshold limits.
There can be "n" number of reasons for signal delay. The key factor is impedance control. Try to analyze your digital signal with respect to its rise time...convert rise time to critical length.... and based on that you can quantify whether the adjacent ground layer causes any signal delay or not.
An adjacent ground layer always provides good decoupling between signal layers and a good reference point for the signals.