Will Altera Cyclone PLL support such clocks?

[michahamod]

Altera Cyclone PLL

Does anyone know if cyclone PLL is support the following:
Input clock : 32.4 Mhz
Output clk0 ; 32.4 Mhz (same to input and align to it)
Output clk1: 10.8Mhz (input /3, align to input)

In quartus II ver 2.2 (SP2) its seems OK , but in quartus II ver 3.0 (SP2)
I get from mega wizard that this PLL can not be implemented.

 

[drwho78]

Re: Altera Cyclone PLL

Your PLL cannot be implemented in Cyclone. In SP2, the megafunction bug is fixed. With Cyclone PLL, the minimum VCO frequency is 300 MHz and Maximum frequency is 800 MHz. With an input frequency of 32.4 MHz, the PLL multiplies 32.4 MHz by 16 to get 518.4 MHz. In order to get 10.8 MHz output, the post-scale counter would have to divide by 48. Unfortunately, Cyclone post-scale counter has a maximum of divide by 32.

Your design can be implemented in Stratix, which has a post-scale counter of 512.

With lost-cost FPGAs, you loose some functions.

 

[cd505]

michahamod
u can do it in q3+sp2.
it's easy.

 

[cfft]

Re: Altera Cyclone PLL

I have heard that the PLL in altera fpga devices is not function well.
If you want to use the fration multiple,the performance is not good.
How about the abate ratio of the PLL in altera device?anyone can confirm it?
Thanks!

 

[davorin]

Re: Altera Cyclone PLL

BTW:

Can the c0/c1 outputs from PLL be programmed to be exactly 180 degrees phase shifted? Or are both outputs running independantly?

Need high clocks (> 200MHz) phase shifted to double the RAM write rate (o;

And how can I simulate with a PLL in the design? The simulator synthesizes away the PLL.