Will a register hold value when clock to the register is gated?

[vivek_p]

Will a register hold value when clock to the register is gated. Can anyone explain

 

[shelby]

Registers - Gating

yes.

A registers normal operation is to hold the current value until the next clock edge. All clock gating is, is extending the amount of time between clock edges.

 

[salma ali bakr]

Re: Registers - Gating

This is called Clock Gating and it's one of the power saving methods use in sync designs. Its concept is to switch off some flip flops in certain clock cycles when their operation is not needed. In this case, no switching power is consumed and only leaage currents are present

* There are two types of clock gating schemes:

-- Latch-free:

gated_clk <= clk_ctrl AND clk; -- just ANDing the enable/control signal with the clock

process (gated_clk) -- using the gated clock signal in the process(es) to follow

But the problem is that the enable/control signal may be delayed from the clock rising edge, causing a premature clock (not having the same duty cycle as the original clock), or may be changed multiple times during the high level of the clock causing the generation of multiple clock pulses instead of just one! So the solution would be to try and hold the enable/control signal from the rising edge of the clock till the falling edge, which can be done by a level sensitive element (latch).

-- Latch-based (solves the problem of the latch-free version)

process (clk, enable)
if clk = '0' then
clk_ctrl_new <= clk_ctrl;
end if;
end process; -- that's the latch

gated_clk <= clk_ctrl_new AND clk;