Wide Swing PMOS Cascode Biasing

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Hello,
I would like to know if someone has designed a wide swing PMOS cascode biasing circuit (as attached in the picture) in 16nm FinFET, especially for IO devices having 1.8V supply. I see that theoretically it should be possible to keep M2 in saturation as long as Vov2<= |Vth1|, but practically it is looking impossible to keep M2 in saturation especially at fast hot corners.
Thank you.
 

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Dominik Przyborowski said:
If you saying so it has to impossible...
What are the condition to keep M2 saturated?
What provides voltage on M2 drain?
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As I mentioned, M2's saturation condition is Vov2<= |Vth1|. The drain voltage of M2 and gate voltage of M1 is provided by a current source. The full biasing circuit is attached in the picture below.
It looks like, at fast hot corners, either M1 or M2 could be kept in saturation and the other triodes.
 

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Sorry, misled mosfets indexes.
VGS1 has to be higher than Vdsat1+Vdsat2, what for high temperature means 300mV. And yes, if temperature is 125C then drop of Vth is ca 180mV with extra 50mV due to FF corner.
So, you would like to have device with nominal Vth (in room temp) at least 500mV or go for high inversion level of M1.
Of course, I assuming M3 is providing proper VDS for M1.
What are the voltages in your mirror and threshold voltages?
 

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