Why Zero is coming in this circuit

[pgoyal]

Hello

I have a very very basic que. While doing cascode amplifier I observed one thing

Output impedence of cascode is (NMOS M1 bottom, M2 cascode)

rout = ro1 + ro2 +gm2.ro1.ro2

if there is a cap between M1 & M2
Then zo1 = r01 || 1/sC1 = r01/(1+r01.sC1)

Zout = Zo1 + ro2 + gm2.Zo1.r02
=(r01+r02+gm2.r01.r02) + s.ro1.ro2.C1
------------------------------------------------
1+ s.r01.C1

≈ (1+sC1/gm2)
----------------
(1+s.ro1.C1)
it shows a zero but I am not getting intutive reason behind it.
1) Is there any 2 paths which I am missing
2) there is nothing like half signal

<---Zout
******|
***----
--||****M2
***----
******|--------
**---- *****|
*-||**M1** -------
**----***** ------- C1
****|*******|
****Gnd****Gnd

 

[safwatonline]

try to replace each of the MOS by resistor for a clearer view.

for intuitive understanding, at low frequency u get just Rs, at higher frequency one of the Rs is decreased by the capacitor (that is a pole), at higher frequency the capacitor completely shorts the lower resistor and the effective resistance is the upper one (that is a zero)