why we use set_case_analysis...

[Manochitra]

hi...
what is use of set_case_analysis ?? why we set values 0 ,1 for it? what is the use SCAN_EN?? explain me



thanks in advance

 

[rca]

you could define a sdc file for the scan mode for example with more hold time margin, or different max frequency, and another sdc for functional mode with a highest clock frequency, or with many clocks, instead one in scan mode(for example).
In general, if I could, I prefer to have only sdc constraint with cover scan & functional(s) modes, but sometime you need more than one sdc file.

 

[Manochitra]

hi rca

thank you for ur information..If we set set_case_analysis as 0 or 1 is there any change ?? where could I find this change??

 

[rca]

you should define which net:set_case_analyzis <net> <value>, no?

---------- Post added at 11:19 ---------- Previous post was at 11:19 ----------

if we apply the constant value on the sepcific net like force the chip in scan mode for example

 

[vijayR15]

hai mano,,
By setting set_case_analysis to 1 u are making the tool to add this path in timing analysis

By setting set_case_analysis to 0 u are neglecting in timing consideration

Normally we use this for test case analysis


Ex:-
set_case_analysis 1 Testmode

sometimes to use set_case_analysis u need to initialize the set_interactive_active mode

syntax:- set_interactive_constraint_modes [all_constraint_modes -active]

To know which is used in set_case_analysis

u can use report_case_analysis

This may help you... Thanks