why we need test benches in verilog

[pooja_khubbar]

hello friends
i want to know why we need test benches in verilog..as we can easily check the outputs by forcing values through modelsim..plz explain me the reason...

 

[ckshivaram]

test benches alow you to put define the input of your design and when you run your simulation it will give results according to your input. Like when you want to simulate a counter you can define the cycle of your clock with a test bench file and run it.
test benches are just models those are used to varify correctness of a HDL model so that u can compare o/p response with expected values.According to that timing information u can see wavforms in ur simulation.it is done before ur simulation

 

[aquakeerthi]

actually by force you can do it the thing is test-benches are used to test the code in various condition, for pure testing and analysis part and if you are familiar with model sim it should show some pearl commends it show some successive executed commends so professional analysis it is mandatory,
well it is not right way to force the reg too, still there are some TCL commends are there to regularise simulation of u that i would better and surly you would clarified

# advantage
* specify inputs and observe outputs
* allows testing without downloading to device
*can program a test of all inputs as well automatically check expected behaviour
*Testbench is self-contained
*Internal signals are directly manipulated
Testbench Structure

architecture behaviour of testbench is

signal clk, rst : std_logic;

signal done : boolean;

constant clk_period : time := 5 ns;

begin

end architecture;

done <= true when condition else

false;

. . .

. . .

clk <= '0' when rst = '1' else

not clk after clk_period when not done

else '0';

. . .

rst <= '1',

'0' after time;

Condition indicates simulation is over. e.g:
o time period has elapsed
o iterations completed
o end of input file reached

*
Basic signals are clock, reset, and termination:

Clk:

o not active during reset
o oscillates until done

Reset:

o brief pulse for reset of all signals in the design

 

[bigdogguru]

The following quote from the Art of Writing TestBenches sums it up:

Writing a testbench is as complex as writing the RTL code itself. These days ASICs are getting more and more complex and thus verifying these complex ASIC has become a challenge. Typically 60-70% of time needed for any ASIC is spent on verification/validation/testing. Even though the above facts are well known to most ASIC engineers, still engineers think that there is no glory in verification.

Art of Writing TestBenches

A Verilog HDL Test Bench Primer