Non AMP

why we don't do hold analysis after placement

Thread starter Raghu Chowdary
Start date Apr 15, 2014

Status: Not open for further replies.

Apr 15, 2014

#1

R

Raghu Chowdary

Newbie level 4

we perform only setup timing analysis only after placement ... why dont we do hold timing analysis after placement ?

Apr 16, 2014

#2

R

ro9ty

Member level 4

This thread would help you. Still if you have queries please let me know.
https://www.edaboard.com/threads/205641/

Status: Not open for further replies.

Similar threads

E
Why doesn't clock transition time affect my timing analysis (PrimeTime)?
- Started by EE18
- Aug 15, 2024
- Replies: 8
ASIC Design Methodologies and Tools (Digital)
E
Why Do Negative Delays Occur in Timing Reports and What Do They Mean?
- Started by edadl
- Oct 1, 2024
- Replies: 2
ASIC Design Methodologies and Tools (Digital)
R
Hold values
- Started by randomname56
- Jul 23, 2024
- Replies: 6
ASIC Design Methodologies and Tools (Digital)
J
question on power analysis, after synthesize the verilog RTL model
- Started by jj00510
- Apr 18, 2024
- Replies: 3
ASIC Design Methodologies and Tools (Digital)
C
TSMC65LP DRC errors after sealring addition
- Started by celuk
- Sunday at 3:19 AM
- Replies: 5
ASIC Design Methodologies and Tools (Digital)