Why we are setting uncertainity , latency in sdc file

[engsakthimani@gmail.com]

i am doing synthesis ...... please can any one explain why we are setting uncertainity and latency and why we are setting set_false_path and multicycle path

 

[vimalraj205]

hai



set_clock_uncertainty, adds the extra padding to both the setup and hold

calculations to every path in the design. During synthesis set_clock_uncertainty is used

to account for delay between the clock branches (skew). A designer can use this fact to

over constrain the design during synthesis and relax the constraint during timing closure

to ensure that the design will meet timing when physical design is complete

 

[vijayR15]

Hai mani,

clock uncertainity deals with clock skew, jitter and syntheis margin...........

clock latency is source latency + network latency...

falsepath is setted for some ports...... not to take that path into an account of STA

multicycle path is for making the data to capture in two or more clock.... increasing the time period...

Hope this may be usefull.. Thanks:razz:

 

[yadavvlsi]

Clock uncertainty accounts for clock skew, clock Jitter and margins.

False path is that timing path for which STA tool is instructed to ignore its timing requirements (setup, hold). Typically false paths are present in the design because of the following reasons.
1) The path is functionally never exercised.
2) There are some unused ports of a reused IP which form these false paths.
3) Synthesis tool introduced flip-flops which break inadvertent combinational loops in the design which cause false paths.
4) Control signals that aid in the testability of the design should not be constrained during normal mode of operation, so mark them as false paths.

Multi-cycle path is one which takes more than one clock cycle to complete its operation. For example, an FSM produces enable signal for every 3 clock cycles and the o/p of a register is to samples only when this enable is high. So, this path having the register has to be declared as multi-cycle path in synthesis constraints. The input to this path should not change through out these 3 cycles.

ASIC-SoC-VLSI Design: Clock Definitions