Why via size is bigger tha via exact size DRC rule ?

[vardan]

Via exact size DRC rule

Hi all,

What problems may be encountered during manufacturing if via size is bigger than noted by "exact size DRC rule"? What caused that constraint?

Vardan

 

[ambreesh]

Re: Via exact size DRC rule

Usuall related to yeild

 

[vardan]

Re: Via exact size DRC rule

Dear ambreesh,
I understand that if via is smaller than prescribed by DRC rules, yield will be lower.
But what's wrong if I make it twice bigger?

vardan

 

[ceyjey]

Re: Via exact size DRC rule

Hi, Vardan,
The problem with the large via or contact is that it can lead to manufacturing defects during chemical mechanical polishing.
-----**---------------------------------------********--------------------
\\\\\\*////////////// <-metal \\\\\\\\\\\\\\\ ******///////////////// <- metal
-----| |--------------------------------------| \_____/ |---------------------
-----| |---------------------------------------|______|----------------------
After CMP, the metal on the edge of vias is very thin and fragile. Even if it is not broken during manufacturing, this area is very sensitive to electronic migration effect. Hence, the chip is not robust enough to sustain a long time running.
So the guideline is using the recommended size for the via, duplicating it to form a matrix when needed.

Hope this helps

ceyjey

 

[vardan]

Re: Via exact size DRC rule

Thanks for help, Ceyjey.
But now I don't understand other thing. Big vias are used in IO pads. Metal layers in pads cannot be thin as they undergo some mechanical stressing too. How this problem is overcomed in that case?

vardan

 

[ceyjey]

Re: Via exact size DRC rule

In my personal experience, the vias in IO pad are no larger than standard vias. They are generally grouped into a diamond-shaped array to allow more current flow.
Also, there are several things I think might be helpful to you.
First, the size of standard via grows as the metal layer level increases.
Second, vias can be stacked in contemporary processes. That is, the via from metal2-to-metal3 can be directly on the via metal1 to metal 2.
Third, generally speaking, all available metals have to be used in IO pads.

Correct me if I am wrong, thank you

ceyjey

 

[vardan]

Re: Via exact size DRC rule

Hi Ceyjey,
There is nothing to correct about “stacked-via” processes. And I know too little about IO pads at the moment. Thanks for your response.

vardan

 

[vumn]

Re: Via exact size DRC rule

Hi,
each via is modeled as a resistor and it's resistance has been determined for each process. If via size is free to draw, the resistance of via becomes variable. The model for each devices is no longer correct. So via is better drawn in a certain size.
Hope this helps.

 

[xiongshoufen]

Via exact size DRC rule

you can find the explaination from the analog book of razavi :


Figure 17.12