Why vds != id * (1/gds) in HSPICE?

gds vds

Hi, All:

After checking the HSPICE output of the operating points, I am puzzled to find out that vds is not equal to id * (1/gds), why is that? Also, the threshold voltage vth is not the same as the one from the model card even when vbs=0.

Thanks,

hspice gds

if your tech is 0.35 and less then it is due to many effects including short channel effect.
hock

vds id

hyc said:

Hi, All:

After checking the HSPICE output of the operating points, I am puzzled to find out that vds is not equal to id * (1/gds), why is that? Also, the threshold voltage vth is not the same as the one from the model card even when vbs=0.
Thanks,

Click to expand...

What is your gds ? Transconductance (gm) or 1/rds ?

gds transconductance

I am using 0.18 technology and here is a partial report, thanks,

subckt
element <====>0:m15<====>0:m16<====>0:m17
model <======>0:nch<======>0:nch<====>0:nch
region<====>Saturati<====>Saturati <====>Saturati
id <======>24.6192u<====>25.3348u<====>25.0000u
ibs <======>0.<======>0.<======>0.
ibd <======>0.<======>0. <======>0.
vgs <====>880.2636m<====>880.2636m<====>880.2636m
vds <====>648.7531m<====>1.1246<====>880.2636m
vbs <====>0. <====>0.<====>0.
vth <====>440.1654m<====>436.2748m<====>438.2727m
vdsat <====>298.8367m<====>301.0420m<====>299.9099m
vod<====>440.0982m<====>443.9888m<====>441.9909m
beta <====>368.9142u<====>368.9623u<====>368.9379u
gam eff<====>578.6609m<====>578.6609m<====>578.6609m
gm <====>101.4369u<====>103.5968u<====>102.7308u
gds <====>1.9318u<====>1.3051u<====>1.4612u
gmb <====>25.8913u<====>26.3499u<====>26.1712u
cdtot<====>2.2333f<====>2.1007f <====>2.1611f
cgtot<====>2.3608f<====>2.3590f<====>2.3595f
cstot <====>4.4153f<====>4.4156f<====>4.4155f
cbtot<====>4.7626f <====>4.6350f <====>4.6946f
cgs <====>1.9991f <====>1.9992f <====>1.9992f
cgd <====> 256.1732a<====>254.2813a<====>254.6808a

gds, transconductance

I would expect vds to equal id * (1/gds) while the transistor is in triode region. In this region, the transistor behaves like a resistor and this is why that equation holds. shown in the picture, while in triode, the transistor behaves as your equation describes.

Once the transistor enters saturation, Ids still scales with vds, but at a different rate since 1/gds changes. This change in the output impedance is a non-linear effect that cannot be modeled with the linear equation you have shown. However, if you really needed to, you can write 2 piece wise linear equations to model the case 1, when the transistor is in triode, and case 2 when the transistor is saturated.

Also... keep in mind that gds is a small signal parameter while Vds and Ids are large signals.

eecs4ever:

Thank you for your reply.
As you said, Vds and Ids are large signals, since KVL always holds, so Vds must equal to Ids * R, I wonder then what this R is, and if there is any relationship between R and gds. (Intuitively, even if they are differnt, shouldn't they be very close?)
Also, how do I come up with the second piece equation to represent the transistor in saturation?

Thanks,

hyc said:

eecs4ever:

Thank you for your reply.
As you said, Vds and Ids are large signals, since KVL always holds, so Vds must equal to Ids * R, I wonder then what this R is, and if there is any relationship between R and gds. (Intuitively, even if they are differnt, shouldn't they be very close?)
Also, how do I come up with the second piece equation to represent the transistor in saturation?
Thanks,

Click to expand...

I assume gds is the small signal drain-source conductance (remember my question some days ago) and Vds, Ids are large signal parameters,
(CORRECTION: DC PARAMETERS !)
Then, in the saturation region R is simply a dc resistance corresponding to the inverse slope of the line between the origin and the actual bias point (in triode region R≈1/gds).
But there is no relation between R and gds in the saturation region.

Hi, LvW:

Thank you for the reply.
Attached please find two pages which I yanked from the book "Tradeoffs and Optimization in Analog CMOS Design" by David Binkley, please refer to eq. (3.52), is the gds the same small signal reported from HSPICE output? Also, please refer to Figure 3.34, in which I add a red line from the bias point to the origin, is the slope of the red line 1/R that we are talking about in the above messages?

Thanks,

hyc said:

Hi, LvW:
Thank you for the reply.
Attached please find two pages which I yanked from the book "Tradeoffs and Optimization in Analog CMOS Design" by David Binkley, please refer to eq. (3.52), is the gds the same small signal reported from HSPICE output? Also, please refer to Figure 3.34, in which I add a red line from the bias point to the origin, is the slope of the red line 1/R that we are talking about in the above messages?
Thanks,

Click to expand...

Yes, exactly !
The term gds is the slope of the curve Id(VDS) in the saturation region. And the Early voltage is a fictive voltage (and cannot be measured) which helps to describe and model this conductance.
The resistor R as defined by the red line in the figure has no real practical meaning - it is just the ratio of two dc values.
Regards

LvW:

Thank you very much. Really appreciate your clarification.