Why use pulse transformer drive for bottom FETs in Bridge type SMPS's?

[treez]

Hello,
In Full Bridge SMPS type converters, why do people use pulse transformers on the bottom FET drives as well as the hi side FET drives?
I mean, presumably its so that the propagation delay of the switching signal is equal for both top and bottom FETs, but isn’t this pointless? The 70ns or so delay is too short to be of any relevance…

..Consider the attached LLC converter simulation, (LTspice) which shows one LLC converter with delay of 70ns between top and bottom FETs, and another LLC which has no delays…..you can see that there is no disadvantage whatsoever of having the delay.

So why use pulse transformers on top and bottom on full bridge SMPS’s or Full bridge LLC SMPS’s?

 

[Warpspeed]

Two reasons.
It ensures the upper and lower mosfets receive the EXACT same drive waveforms and switch at the exact same times. If you use a totally different drive circuit, that may be more difficult to achieve.
And its simple and economic, because the pulse transformer is needed anyway for the upper mosfet, so adding a third winding is pretty much something for nothing..

The other reason is it isolates the power ground from the ground on the driver circuit board. Often the power ground can be very noisy, and this can help with that particular problem.

A third reason can be fault escalation. If one or more power mosfets go *BANG* whatever drives a pulse transformer usually survives.
That is often not the case with a gate driver chip. If the main power supply which can be at hundreds of volts gets back into the +12v supply because a mosfet and gate driver chip blew, the damage can be catastrophic.

 

[treez]

Thanks..i am sure however, that you will be aware of the following..

It ensures the upper and lower mosfets receive the EXACT same drive waveforms and switch at the exact same times

..I don’t think it matters that they switch at slightly different times. We’re talking around 70-100ns difference at most…insignificant. As in the above simulation, it really makes no difference. There is no fault caused by such a delay.

so adding a third winding is pretty much something for nothing

..i see your point, but its still extra work to wind in the third winding, and when there’s no need for it, why do it?

The other reason is it isolates the power ground from the ground on the driver circuit board. Often the power ground can be very noisy, and this can help with that particular problem.

..The 1EDI60N FET driver from infineon can do this, and doesn’t need the hassle of the pulse transformer to do it.

1EDI60N FET Driver datasheet..
https://www.infineon.com/dgdl/Infin...N.pdf?fileId=db3a3043427ac3e201428e5da08f372a

A third reason can be fault escalation. If one or more power mosfets go *BANG* whatever drives a pulse transformer usually survives.
That is often not the case with a gate driver chip. If the main power supply which can be at hundreds of volts gets back into the +12v supply because a mosfet and gate driver chip blew, the damage can be catastrophic.

..Again, the 1EDI60N FET driver can guard against this…but anyway, if the fets do go bang, then the power supply is done for, who cares what happens to it after that?

 

[Warpspeed]

Ah yes, but your 1EDI60N FET driver requires isolated dc power, a pulse transformer does not.

Pulse transformer is not always the ideal solution, but for low cost, simplicity, and robustness, its often a pretty good choice, particularly where the duty cycle is pretty much fixed at 50%.

I have NEVER thrown away a complete power supply of my own design just because a mosfet bombed out.

 

[treez]

Ah yes, but your 1EDI60N FET driver requires isolated dc power, a pulse transformer does not.

I agree but as you know, this isn't relevant to the question of the top post. Also, you can put a FET drive IC near to a FET and send a signal to it from a PWM controller.......and the high current pulse just comes from the output of the fet driver , which is near the fet.

Consumer power supplies, as you know, will not generally get fixed if a fet blows up inside them. They will be thrown away.

- - - Updated - - -

Ah yes, but your 1EDI60N FET driver requires isolated dc power

.....actually the 1edi60n doesn't "necessarily" need an isolated power source. In any case, I think we can agree(?) that the delay caused by driving the bottom fets directly is insignificant, and so cannot be the reason for using pulse transformer drive for the bottom fets of a bridge type SMPS, as well as the top FETs.

- - - Updated - - -

by the way I did like your point about the fact that the pulse transformer isolates you away from the noisy ground, or at least, can be used for this purpose. It is the best way to do that, and though of course, you can also do it by careful grounding strategy, and diff pair routing of drive signals.

 

[Warpspeed]

So why use pulse transformers on top and bottom on full bridge SMPS’s or Full bridge LLC SMPS’s?

I gave several reasons, why.

Not all switching power supplies are fitted to cheap mass produced consumer crap.

Sometimes very expensive top end professional equipment is involved, and if you are designing for that, your career will not go far if your designs become known to suffer from cascade catastrophic failure.

Serviceability and ease of repair are fundamental to good design.

 

[treez]

Thanks, but surely in your assessment of power supplies which can fail , you do not include the delay between top and bottom fet's switching as a possible failure mechanism?....I mean, if all fets are "not" supplied by the same pulse transformer type drive, the bottom fets will switch on some 100ns before the top fets, and switch off some 100ns before the top fets go off, but this is insignificant and will never cause failure, surely you agree with that premise?

 

[Warpspeed]

Cross conduction is always something to be very well aware of.

Nothing wrong with driving a full bridge with two transformers connected to diagonal pairs. Or even a single winding connected to P an N mosfets with the gates and sources directly paralleled.

Another technique is the fast off/ slow on method, using a gate resistor shunted by a diode.
Quite a few ways to design simple effective gate drive circuits with pulse transformers, but it does all need to be thought through very thoroughly.
There definitely are potential problems to avoid, no argument there.

 

[treez]

Cross conduction is always something to be very well aware of.

Thanks, though you agree that cross conduction does not happen from the simple delay spoken of here, nor any other problems?

 

[Warpspeed]

I suppose it depends what the gate delays and rise/fall times are.
An extra 70nS asymmetry is certainly not much, but it still needs to be considered.